公开(公告)号：EP1082732A4

公开(公告)日：2006-11-22

申请号：EP00906973

申请日：2000-01-20

Applicant: MOTOROLA INC

Inventor： LEE TIEN ,  LACH LAWRENCE ,  DUNN GREGORY J

IPC: H05K1/16 ,  H01C1/01 ,  H01C7/00 ,  H01C17/06 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

公开(公告)号：EP1090401A4

公开(公告)日：2004-04-28

申请号：EP99964048

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H01L21/822 ,  H01L27/04 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H01G4/10

CPC classification number: H05K1/162 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/09509 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions, for example, for producing integral capacitors (32), generally entails providing a substrate (10) with a first conductive layer (12), forming a dielectric layer (14) on the first conductive layer, and then forming a second conductive layer on the dielectric layer (16). A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

公开(公告)号：EP1053507A4

公开(公告)日：2002-07-24

申请号：EP99939643

申请日：1999-06-29

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON

IPC: G03F7/00 ,  H01C17/06 ,  H01C17/07 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/38 ,  G03C5/00

CPC classification number: H05K1/167 ,  G03F7/00 ,  H01C17/07 ,  H05K3/0023 ,  H05K3/025 ,  H05K3/048 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/1461

Abstract: A method for manufacturing a microelectronic assembly to have a resistor (12) on a circuit board (10). The method entails applying a photosensitive dielectric to a substrate (18) to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion (22). An electrically resistive film (14) is then applied to the dielectric layer and the dielectric layer is developed so that a portion of the resistive film remains over the second portion to form the resistor. A second dielectric layer (32) is then applied, photoimaged and developed to form openings (34). Terminations (16) can then be formed in the openings by known plating techniques. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or other nickel alloy and a sacrificial backing such as a layer of copper.

Abstract translation: 一种用于制造微电子组件的方法有一个电阻器，并且特别是金属电阻片，具有期望的加工和尺寸特性。 该方法基因反弹需要施加光敏介电到基材以形成介电层。 该介电层被成像的照片，以在基片上的第一区域中聚合所述介电层的第一部分，留下所述电介质层的未聚合的剩余部分。 然后电阻性电影被施加到介电层和所述介电层被显影以它们的同时除去未聚合部分和的部分中的电阻膜，覆盖在该未聚合部分，如图在第二部分做了电阻膜-遗体的一部分 以形成电阻器。 另一种方法是为了应用电阻膜-前介电层暴露于辐射，然后通过电阻电影暴露介电层。 所述电阻优选膜是多层膜，没有包括电阻层，颜色：诸如NiP的，镍铬或另一种含镍基合金，和牺牲背衬：如铜层。

公开(公告)号：EP1082882A4

公开(公告)日：2005-10-12

申请号：EP00923062

申请日：2000-01-18

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  ZHANG MIN-XIAN ,  SAVIC JOHN

IPC: H01C1/032 ,  H01C7/00 ,  H01C17/06 ,  H05K1/09 ,  H05K1/16 ,  H05K3/38 ,  H01L21/302

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  H05K2203/0723 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/4913

Abstract: Printed circuit boards (6) with integral high and low value resistors (2 and 4) are efficiently produced. The method of their manufacture entails applying a first layer of a low resistance material (8) onto a dielectric substrate (6) in a predetermined thickness and pattern. The pattern defines the electrical lengths and widths of low value resistors (2), as well as pairs of terminal electrode pads (28 and 30) for the high value resistors (4). A second layer of a high resistance material (18) is applied between and in contact with the top surfaces of the facing ends of each member of the terminal pad pairs (28 and 30). The fixed lengths, widths and thicknesses of the patterned high resistance material determine the values of the high value resistors. Conductive metal terminals are provided at the ends of the low value resistors and at the distal ends of the high value resistor pad to complete the resistors.

公开(公告)号：EP1062849A4

公开(公告)日：2004-08-25

申请号：EP99964046

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/0082 ,  H01F17/0013 ,  H01F41/041 ,  H01F41/046 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2203/0551

Abstract: A method for fabricating circuit board conductors (24A & 24B) generally entails forming a metal layer (24) on a positive-acting photodielectric layer (22), and etching the metal layer to form at least two conductor traces (24A & 24B) that cover separate regions of the photodielectric layer while exposing a third region therebetween. The third region of the photodielectric layer is developed using the two traces as a photomask and removed. Thus, the traces are not only separated by a void (30) formed when the metal layer was etched, but are also separated by the opening (32) formed in the photodielectric layer by the removal of the third region of the photodielectric layer. A ferrite-filled polymer may also be deposited in the void and opening to form a ferrite core (34). Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：EP1629509A4

公开(公告)日：2009-10-21

申请号：EP04775972

申请日：2004-05-11

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  SAVIC JOVICA

IPC: H05K1/16 ,  H01C1/012 ,  H01C7/00 ,  H01C17/065 ,  H05K1/02 ,  H05K1/09 ,  H05K3/12

CPC classification number: H01C17/065 ,  H01C7/005 ,  H05K1/0266 ,  H05K1/095 ,  H05K1/167 ,  H05K3/12 ,  H05K2201/09781 ,  H05K2203/1453

公开(公告)号：EP1695360A4

公开(公告)日：2009-06-03

申请号：EP04813997

申请日：2004-12-14

Applicant: MOTOROLA INC

Inventor： CROSWELL ROBERT T ,  DUNN GREGORY J ,  LEMPKOWSKI ROBERT B ,  TUNGARE AROON V ,  SAVIC JOVICA

IPC: H05K1/16 ,  H01G20060101 ,  H01G4/12 ,  H01G4/33 ,  H05K3/00 ,  H05K3/02 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.