公开(公告)号：EP1187520A2

公开(公告)日：2002-03-13

申请号：EP01121380.8

申请日：2001-09-06

Applicant: Visteon Global Technologies, Inc.

Inventor： Jairazbhoy, Vivek Amir ,  Pham, Cuong Van ,  Glovatsky, Andrew Z. ,  Krautheim, Thomas Bernd ,  Belke, Robert Edward, Jr.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4084 ,  H05K1/056 ,  H05K3/062 ,  H05K3/4092 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2203/0195 ,  H05K2203/063 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49156

Abstract: The present invention discloses a multi-layer circuit board assembly having a first circuit portion having a top surface and a bottom surface a first pre-circuit assembly which is attached to the top surface of the first circuit portion and which includes a top conductive layer. A second pre-circuit assembly is attached to the bottom surface of the first circuit portion and includes a bottom conductive layer. An aperture is formed through the first circuit portion, the first pre-circuit assembly and the second pre-circuit assembly. A plurality of tab portions are integrally formed from the top conductive layer, which extend through the aperture and which are coupled to the bottom conductive layer.

Abstract translation: 本发明公开了一种多层电路板组件，其具有具有顶表面的第一电路部分和底部表面，其被附接到所述第一电路部分的顶表面，并包括一顶导电层的第一前置电路组合件。 第二预制电路组件附接到第一电路部分的底表面并且包括底部导电层。 通过第一电路部分，第一预电路组件和第二预电路组件形成孔。 多个接片部分由顶部导电层整体形成，其延伸穿过孔并耦合至底部导电层。

公开(公告)号：EP1026928A2

公开(公告)日：2000-08-09

申请号：EP00300553.5

申请日：2000-01-26

Applicant: Ford Motor Company

Inventor： Goenka, Lakhi Nandial

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H05K3/062 ,  H05K3/4685 ,  H05K2201/0361 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09736 ,  H05K2201/09772 ,  H05K2201/098 ,  Y02P70/611

Abstract: An etched tri-metal-layer air bridge circuit board specially designed for fine-pitch applications, comprising:

an electrically insulative substrate surface (10), a plurality of tri-metal-layer bond pads (12) arranged in a generally straight row on the substrate surface (10) wherein the row defines a width direction therealong, and a circuit trace (20) arranged on the substrate surface (10), wherein the circuit trace (20) runs between two adjacent ones (22) of the plurality of tri-metal-layer bond pads (12). Each bond pad (12) comprises: (1) a bottom layer (14) attached to the substrate surface (10), the bottom layer (14) being made of a first metal and having an overall width W1 as measured along the width direction; (2) a top layer (18) disposed above and generally concentric with the bottom layer (14), the top layer (18) being made of the first metal and having an overall width W2 as measured along the width direction; and (3) a middle layer (16) made of a second metal connecting the bottom layer (14) and the top layer (18). The bond pads (12) are specially shaped such that W2 > W1 for at least the two adjacent bond pads (12), thus enabling the circuit trace (20) to be spaced closely to the bottom layers (14) of the two adjacent bond pads (12), while allowing the top layers (18) of the pads (12) to be made much larger so as to avoid delamination thereof from their associated middle layers (16).

Abstract translation: 蚀刻的三金属层的空气桥电路板专为细间距应用，包括：在一个基因的反弹直排布置在电绝缘衬底表面（10），的三金属层接合垫有多个（12） 配置于该基板表面（10）worin的电路迹线（20）在基片上表面（10）worin行有沿定义的宽度方向，和一个电路迹线（20）的所述多个相邻的两个（22）之间延伸 三金属层接合焊盘（12）。 每一接合垫（12）包括：（1）附连到基板表面（10）的底层（14），底层（14）由第一金属制成的，并沿宽度方向测量的具有总宽度W1 ; 上述（2）和基因反弹同心设置为与底层（14），所述顶层（18）的顶层（18）由所述第一金属的，并具有为沿宽度方向测量的总宽度W2; 和（3）由第二金属制成的连接底部层（14）和顶层（18）的中间层（16）。 的键合焊盘（12）被特殊形状搜索做W2> W1，至少在两个相邻的键合焊盘（12）从而使电路迹线（20）被紧密间隔相邻的两个键的底层（14） 垫（12），同时允许所述垫（12）的顶层（18），以进行大得多，以便从它们相关联的中间层（16），其避免脱层。

公开(公告)号：EP1111975B1

公开(公告)日：2008-04-02

申请号：EP99931469.3

申请日：1999-07-22

Applicant: Toyo Kohan Co., Ltd.

Inventor： SAIJO, Kinji, Toyo Kohan Co., Ltd. ,  YOSHIDA, Kazuo, Toyo Kohan Co., Ltd. ,  OHSAWA, Shinji, Toyo Kohan Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/062 ,  H05K3/20 ,  H05K3/44 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10S428/901 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/24917

公开(公告)号：EP1500136A1

公开(公告)日：2005-01-26

申请号：EP03710159.9

申请日：2003-04-08

Applicant: Koninklijke Philips Electronics N.V.

Inventor： KLOEN, Hendrik, K. ,  STEENBRUGGEN, Gerardus, H., F., W. ,  VAN DE WATER, Peter, W., M.

IPC: H01L23/31 ,  H01L21/48

CPC classification number: H05K3/062 ,  H01L21/4821 ,  H01L21/4828 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/185 ,  H05K2201/0361 ,  H05K2203/0384 ,  H05K2203/1469 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The semiconductor device (10) comprises a carrier (30) and a semiconductor element (20), such as an integrated circuit. The carrier (30) is provided with apertures (15), thereby defining connecting conductors (31-33) having side faces (3). Notches (16) are present in the side faces (3). The semiconductor element (20) is enclosed in an encapsulation (40) that extends into the notches (16) in the carrier (30). As a result, the encapsulation (40) is mechanically anchored in the carrier (30). The semiconductor device (10) can be made in a process wherein, after the encapsulating step, no lithographic steps are necessary.

公开(公告)号：EP1187519B1

公开(公告)日：2004-04-21

申请号：EP01121371.7

申请日：2001-09-06

Applicant: Visteon Global Technologies, Inc.

Inventor： Shi, Zhong-You (Joe) ,  Glovatsky, Andrew Z. ,  Goenka, Lakhi N.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4038 ,  H05K3/062 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09581 ,  H05K2203/1438 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

公开(公告)号：EP1204303B1

公开(公告)日：2003-09-17

申请号：EP01125894.4

申请日：2001-10-30

Applicant: Visteon Global Technologies, Inc.

Inventor： Achari, Achyuta ,  Baker, Jay D. ,  Paruchuri, Mohan R. ,  Nation, Brenda Joyce ,  Goenka , Lakhi Nandlal ,  Stoica, Vladimir

IPC: H05K1/09 ,  H05K3/02 ,  B23K20/04

CPC classification number: H05K3/022 ,  B32B15/017 ,  B32B15/018 ,  H05K2201/0361 ,  Y10T29/49126

公开(公告)号：EP0929208A3

公开(公告)日：2003-02-12

申请号：EP99300207.0

申请日：1999-01-12

Applicant: Ford Motor Company

Inventor： Zitzmann, Alice Dawn ,  McLeskey, Edward P. ,  Belke, Robert Edward, Jr. ,  Trublowski, John

IPC: H05K3/46 ,  H05K3/40 ,  H05K3/44 ,  H05K3/00

CPC classification number: H05K3/4046 ,  H05K1/0393 ,  H05K1/056 ,  H05K3/0058 ,  H05K3/022 ,  H05K3/3447 ,  H05K3/386 ,  H05K3/403 ,  H05K3/4084 ,  H05K3/4092 ,  H05K3/445 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/4632 ,  H05K3/4635 ,  H05K3/4685 ,  H05K2201/0129 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/10303 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: A method of manufacturing an improved multi-layer printed circuit assembly having at least two conductor patterns. The method includes providing a first layer (12) having a first metal surface a second layer (14) having a second metal surface. A thin flexible carrier (16) is placed between the first (12) and second (14) layers. The first (12) and second (14) layers are attached to opposite surfaces of the carrier (16). The first and second metal surfaces are etched (22) to form first and second conductor patterns. The conductor patterns form the electrical traces interconnecting components on an electronic circuit assembly. The first and second conductor patterns are electrically connected to form an electronic circuit assembly that includes electronic traces on both sides of the circuit board.

Abstract translation: 制造改进的多层印刷电路的制造方法组件，其具有至少两个导体图案。 该方法包括：提供具有第一金属表面具有第二金属表面上的第二层的第一层。 薄的柔性载体在第一层和第二层之间放置。 所述第一层和第二层附接到所述载体的相对的表面。 第一和第二金属表面被蚀刻，以形成第一和第二导体图案。 导体图案形成的电迹线的电子电路组件的互连组件。 第一和第二导体图案电连接，以在电子电路组件做包括在所述电路板上的电子bothsides痕迹。

公开(公告)号：EP1187520A3

公开(公告)日：2003-01-15

申请号：EP01121380.8

申请日：2001-09-06

Applicant: Visteon Global Technologies, Inc.

Inventor： Jairazbhoy, Vivek Amir ,  Pham, Cuong Van ,  Glovatsky, Andrew Z. ,  Krautheim, Thomas Bernd ,  Belke, Robert Edward, Jr.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4084 ,  H05K1/056 ,  H05K3/062 ,  H05K3/4092 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2203/0195 ,  H05K2203/063 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49156

Abstract: The present invention discloses a multi-layer circuit board assembly (10) having a first circuit portion (12) having a top surface and a bottom surface. A first pre-circuit assembly (24) is attached to the top surface of the first circuit portion (12) and includes a top conductive layer (22). A second pre-circuit assembly (32) is attached to the bottom surface of the first circuit portion (12) and includes a bottom conductive layer (30). An aperture is formed through the first circuit portion (12), the first pre-circuit assembly (24) and the second pre-circuit assembly (32). A plurality of tab portions are integrally formed from the top conductive layer (18,22), which extend through the aperture and which are coupled to the bottom conductive layer (12,18).

公开(公告)号：EP1187519A3

公开(公告)日：2003-01-15

申请号：EP01121371.7

申请日：2001-09-06

Applicant: Visteon Global Technologies, Inc.

Inventor： Shi, Zhong-You (Joe) ,  Glovatsky, Andrew Z. ,  Goenka, Lakhi N.

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4038 ,  H05K3/062 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09581 ,  H05K2203/1438 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A method for forming connections within a multi-layer electronic circuit board (40). The method includes forming an aperture (32) within the circuit board and selectively coating the interior surface of the aperture (32) with a polar solder mask material (42) that is effective to bond with solder that is selectively inserted into the aperture (32), thereby retaining the solder within the aperture (32) and improving the electrical connection between tab (33) and metal layer (26) provided by the solder.

Abstract translation: 一种用于在多层电子电路板（40）内形成连接的方法。 该方法包括在电路板内形成孔（32）并且用极性阻焊掩模材料（42）选择性地涂覆孔（32）的内表面，该材料有效地与选择性地插入孔（32 ），由此将焊料保持在孔（32）内并且改善由焊料提供的接头（33）和金属层（26）之间的电连接。

公开(公告)号：EP1248503A1

公开(公告)日：2002-10-09

申请号：EP00987672.3

申请日：2000-12-21

Applicant: Toyo Kohan Co., Ltd.

Inventor： SAIJO, Kinji, C/o Toyo Kohan Co., Ltd. ,  OHSAWA, Shinji, C/o Toyo Kohan Co., Ltd. ,  OKAMOTO, Hiroaki, C/o Toyo Kohan Co., Ltd. ,  YOSHIDA, Kazuo, c/o Toyo Kohan Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K1/0221 ,  H05K3/062 ,  H05K3/4647 ,  H05K2201/0361 ,  H05K2201/09254 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A structure of a multilayer printed wiring board having a wiring lead-out port can be easily formed. A large number of products can be easily manufactured with good size reproducibility. A method of manufacturing the same is also disclosed. The multilayer printed wiring board is characterized by having a signal circuit conductor perfectly covered by an earth circuit in its inside and wiring lead-out port. A signal circuit conductor having a branch pattern is preferable. The multilayer printed wiring board is manufactured by selectively etching the copper of a cladding sheet manufactured by bonding a copper foil to a nickel foil with 0.1-3% reduction ratio and forming a signal circuit conductor perfectly covered by an earth circuit and the wiring lead-out port.

Abstract translation: 多层印刷线路板的特征在于具有完全被其内部的接地电路覆盖的信号电路导体和布线引出端口。 具有分支图案的信号电路导体是优选的。 多层印刷线路板是通过选择性地蚀刻通过将铜箔接合到镍箔上而制成的包覆片的铜而制成的，该镍箔具有0.1-3％的电流并形成完全被接地电路覆盖的信号电路导体和布线引出 港口。