公开(公告)号：EP1482771B1

公开(公告)日：2018-11-28

申请号：EP04012773.0

申请日：2004-05-28

Applicant: DOWA METALTECH CO., LTD.

Inventor： Tsukaguchi, Nobuyoshi ,  Kosaka, Michihiro

IPC: H05K3/06 ,  C23F1/20 ,  C04B37/02

CPC classification number: H05K1/0265 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/126 ,  C04B2237/128 ,  C04B2237/366 ,  C04B2237/402 ,  C04B2237/64 ,  C04B2237/704 ,  C04B2237/706 ,  C23F1/20 ,  H01L21/4867 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/067 ,  H05K2201/098 ,  H01L2924/00

Abstract: Producing metal/ceramic circuit board comprises forming metal layer on side(s) of ceramic substrate (10) and resist on metal layer, then etching and removing portion of metal layer with etchant of mixed solution. The metal layer contains aluminum as principal component. The resist layer is shaped. The etchant of mixed solution is prepared by mixing ferric chloride with water without adding any acids to form metal circuit on ceramic substrate side(s). An independent claim is included for metal/ceramic circuit board comprising ceramic substrate and metal circuit plate (12) on side(s) of the substrate. The metal circuit plate has skirt spreading length of = 200 Micro on peripheral edge of the metal circuit plate. The corrugated is the maximum distance between straight lines parallel to the linear peripheral edge of the metal circuit plate to be formed. The metal circuit plate has skirt spreading length of = 200 Micro. The ratio of skirt spreading length to the thickness of the metal circuit plate is = 0.5. The skirt spreading length is a distance between a plane perpendicular to the principal plane of the metal circuit plate at one end of the bottom face of the metal circuit plate on the same side as one end of the bottom face of the metal circuit plate. The distance is positive when bottom face has greater area than the top face.

公开(公告)号：EP2745656B1

公开(公告)日：2018-09-05

申请号：EP12732572.8

申请日：2012-06-18

Applicant: Robert Bosch GmbH

Inventor： DAUB, Martina ,  BRETTSCHNEIDER, Thomas ,  DORRER, Christian

IPC: H05K3/04

CPC classification number: H05K3/046 ,  H05K1/036 ,  H05K3/027 ,  H05K3/4084 ,  H05K2201/0129 ,  H05K2201/09363 ,  H05K2201/098 ,  H05K2201/2072 ,  H05K2203/107 ,  H05K2203/1581

公开(公告)号：EP2656702A4

公开(公告)日：2018-03-07

申请号：EP11850595

申请日：2011-12-23

Applicant: LG INNOTEK CO LTD

Inventor： LEE SANG MYUNG ,  YOON SUNG WOON ,  LEE HYUK SOO ,  LEE SUNG WON ,  CHUN KI DO

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/202 ,  H05K3/4647 ,  H05K3/465 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/098 ,  H05K2203/0323 ,  H05K2203/0376

Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

公开(公告)号：EP3207771A1

公开(公告)日：2017-08-23

申请号：EP15781900.4

申请日：2015-10-12

Applicant: Heraeus Deutschland GmbH & Co. KG

Inventor： LOOSE, Thomas ,  TURWITT, Martin

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0265 ,  H05K1/0306 ,  H05K2201/0382 ,  H05K2201/09736 ,  H05K2201/098

Abstract: The invention relates to a composite material, comprising a ceramic substrate S having at least one metal layer M on at least one surface of the ceramic substrate S, wherein said metal layer M has a specific shape in the lateral and/or vertical direction. The invention further relates to a corresponding layout of a conducting track and to the use of said layout, to a method for producing at least one conducting track, to a circuit board, and to a stamping and/or embossing tool.

Abstract translation: 本发明涉及一种复合材料，其包括在陶瓷衬底S的至少一个表面上具有至少一个金属层M的陶瓷衬底S，其中所述金属层M在侧向和/或垂直方向上具有特定形状。 本发明进一步涉及导电轨道的相应布局以及所述布局的使用，涉及用于制造至少一个导电轨道，电路板以及冲压和/或压印工具的方法。

公开(公告)号：EP3143847A1

公开(公告)日：2017-03-22

申请号：EP15726023.3

申请日：2015-05-13

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： STAHR, Johannes ,  SCHRITTWIESER, Wolfgang ,  MORIANZ, Mike ,  VOCKENBERGER, Christian ,  LEITGEB, Markus

IPC: H05K1/02 ,  H05K3/40 ,  H05K1/11 ,  H05K1/18 ,  H05K3/12

CPC classification number: H05K1/18 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/09 ,  H05K1/115 ,  H05K1/185 ,  H05K3/10 ,  H05K3/1258 ,  H05K3/40 ,  H05K3/4053 ,  H05K2201/09218 ,  H05K2201/098 ,  H05K2201/09854

Abstract: The invention relates to an electronic device (100) having an electrically insulating support structure (102), an electrically conductive conductor path (104) on a surface of the support structure (102), and an electrically conductive contact structure (106) which extends from the surface into the support structure (102) and is electrically connected to the conductor path (104) at a connection point (108), thereby forming a common conductor track (110). The conductor path (104) and the contact structure (106) transition into each other in an enlargement-free manner at the connection point (108).

Abstract translation: 本发明涉及一种具有电绝缘支撑结构，在支撑结构的表面上的导电导体路径以及从表面延伸到支撑结构中并且电连接到导体路径的导电接触结构的电子设备 在连接点处，从而形成公共导体轨迹。 导体路径和接触结构在连接点处以无放大的方式彼此转变。

公开(公告)号：EP3119169A1

公开(公告)日：2017-01-18

申请号：EP15181783.0

申请日：2015-08-20

Applicant: LG Innotek Co., Ltd.

Inventor： BAE, Yun Mi ,  KWON, Soon Gyu ,  KIM, Sang Hwa ,  LEE, Sang Young ,  LEE, Jin Hak ,  LEE, Han Su ,  JEONG, Dong Hun ,  JEONG, In Ho ,  CHOI, Dae Young ,  HWANG, Jung Ho

IPC: H05K3/10 ,  H05K3/24

CPC classification number: H05K1/11 ,  C25D3/38 ,  C25D3/48 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H05K1/09 ,  H05K3/108 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2203/1184

Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

Abstract translation: 印刷电路板包括绝缘层，绝缘层上的电路图案以及电路图案上的表面处理层。 表面处理层包括具有比电路图案的顶表面的宽度更宽的宽度的底表面。

公开(公告)号：EP2174324B1

公开(公告)日：2017-01-11

申请号：EP07872304.6

申请日：2008-03-18

Applicant: Alpha Metals, Inc.

Inventor： KHASELEV, Oscar ,  DESAI, Nitin ,  MARCZI, Michael, T. ,  SINGH, Bawa

IPC: H01F5/00 ,  B22F9/24 ,  C09D11/00 ,  H05K1/09 ,  H05K3/10 ,  H05K3/24

CPC classification number: H01F5/003 ,  B22F2998/00 ,  C09D11/52 ,  H01L51/0022 ,  H05K3/1241 ,  H05K3/1258 ,  H05K3/38 ,  H05K2201/098 ,  H05K2201/09909 ,  H05K2203/0568 ,  H05K2203/0769 ,  H05K2203/1105 ,  H05K2203/1131 ,  H05K2203/1476 ,  B22F1/0062

公开(公告)号：EP2195829A4

公开(公告)日：2014-01-15

申请号：EP08835327

申请日：2008-10-01

Applicant: KOVIO INC

Inventor： KAMATH ARVIND ,  SCHER ERIK ,  SMITH PATRICK ,  CHANDRA ADITI ,  MOLESA STEVEN

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

公开(公告)号：EP1918632A1

公开(公告)日：2008-05-07

申请号：EP06123475.3

申请日：2006-11-03

Applicant: Asetronics AG

Inventor： Meister, Bruno

IPC: F21L4/00 ,  A61B17/00 ,  F21Y101/02

CPC classification number: F21V21/32 ,  F21W2131/20 ,  F21Y2115/10 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/057 ,  H05K2201/098 ,  H05K2201/10106

Abstract: Die insbesondere für die Verwendung im Medizinalbereich vorgesehene Leuchtvorrichtung weist eine wenigstens eine Leuchtdiode (11) umfassende Leuchteinheit (1) auf, die über elektrische Leitungen (21, 22) mit einer Energieversorgungsvorrichtung (3) verbunden oder verbindbar ist. Erfindungsgemäss ist ein Verbindungselement (2) vorgesehen, das ein streifenförmiges, flexibles und isolierendes Basissubstrat (21) aufweist, das einseitig oder beidseitig mit Metall beschichtet ist, in das die elektrischen Leitungen (22; 23) eingearbeitet sind, die an einem Ende des Verbindungselements (2) zu Anschlüssen (25) der Leuchteinheit (1) und am anderen Ende des Verbindungselements (2) zu Anschlüssen (26) der Energieversorgungsvorrichtung (3) geführt sind, wobei die auf einer oder beiden Seiten des Basissubstrats (21) vorgesehenen Metallschichten (22, 23, 24) derart dimensioniert sind, dass sie das Basissubstrat (21) in einer gewählten Form halten.

Abstract translation: 设备（100）具有带有LED（11）的照明单元（1），并通过电线（22,23）与电源装置（3）连接。 连接单元（2）通过印刷电路板技术制造并且具有涂覆有金属的基底（21）。 线路被引导到连接单元的一端处的照明单元的连接（25）和连接单元的另一端处的电源装置的连接（26）。 金属层（231,232）设置在基板的一侧或两侧并且被设计成尺寸，使得这些层以选定的形式保持基板。

公开(公告)号：EP0935286A4

公开(公告)日：2008-04-09

申请号：EP98921813

申请日：1998-05-26

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： SASAKI KAZUTAKA ,  NAKATA HIROHIKO

IPC: H01L23/12 ,  H01L23/373 ,  H05K1/02 ,  H05K1/03 ,  H05K3/38 ,  H05K1/09

CPC classification number: H05K1/0271 ,  C04B35/111 ,  C04B35/581 ,  C04B35/587 ,  C04B35/62655 ,  C04B37/026 ,  C04B2235/3208 ,  C04B2235/3225 ,  C04B2235/5445 ,  C04B2235/6567 ,  C04B2235/658 ,  C04B2235/723 ,  C04B2235/77 ,  C04B2235/96 ,  C04B2235/9607 ,  C04B2237/122 ,  C04B2237/125 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/407 ,  C04B2237/66 ,  C04B2237/704 ,  C04B2237/708 ,  H01L23/3735 ,  H01L2224/48091 ,  H05K1/0306 ,  H05K3/38 ,  H05K2201/09145 ,  H05K2201/098 ,  Y10T428/12535 ,  Y10T428/12576 ,  Y10T428/24917 ,  H01L2924/00014

Abstract: A highly reliable copper circuit junction substrate which enables a semiconductor chip or a lead frame to be mounted on a ceramic base without causing the base to be broken or deformed by the conventional junction utilizing brazing or copper-copper oxide eutectic, thus accomplishing a junction with a high strength. The substrate is produced by forming on a ceramic base (1) either an intermediate layer (2) comprising a brazing material layer containing chiefly silver and copper containing an active metal or an intermediate layer (2) comprising a first intermediate layer containing the above brazing material layer or a high-melting metal layer and a second intermediate layer containing chiefly nickel, iron and copper and having a melting point of not higher than 1000 °C in order from the side of the base, and forming thereon a conducting layer (3) containing chiefly copper and being shorter by at least 0.05 mm than the intermediate layer in both the direction of length and the direction of width. An outer layer (5) containing chiefly Ni is further formed on the upper surface of the base substrate to give a copper circuit junction substrate. A semiconductor chip is mounted on the above substrate to give a semiconductor device.