公开(公告)号：EP2907191A1

公开(公告)日：2015-08-19

申请号：EP13847868.0

申请日：2013-08-08

Applicant: Raytheon Company

Inventor： BROWN, Andrew K. ,  OBERT, Thomas L. ,  SOTELO, Michael J. ,  GRITTERS, Darin M. ,  BROWN, Kenneth W.

IPC: H01P1/162

CPC classification number: H05K1/167 ,  H05K1/0234 ,  H05K1/0242 ,  H05K3/06 ,  H05K2201/0379 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/09781

Abstract: An apparatus for conveying an electrical signal includes: a conductive pathway having a conductive material. The conductive material has a first edge and a second edge and is configured to convey the electrical signal. The apparatus also includes a resistive material in contact with at least a portion of the conductive pathway, covering an edge of the conductive pathway, and extending beyond the edge. The resistive material has a conductivity less than the conductivity of the conductive material.

公开(公告)号：EP2891390A1

公开(公告)日：2015-07-08

申请号：EP13832479.3

申请日：2013-08-10

Applicant: Inco Innovation

Inventor： BERGLUND, Jan

IPC: H05K1/02 ,  H01B5/02 ,  H02G5/00

CPC classification number: H05K1/181 ,  H05K1/0209 ,  H05K1/0263 ,  H05K2201/0379 ,  H05K2201/10189 ,  H05K2201/10272 ,  H05K2201/1028

Abstract: A power chain consisting of a chain comprising links that are electrically conductive elements mounted on a circuit board in at least two layers and in such a way that the elements included in the power chain are assembled shifted and overlapping and in electrical contact with each other.

公开(公告)号：EP1820235B1

公开(公告)日：2008-07-23

申请号：EP04809026.0

申请日：2004-12-01

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： RIVAS, Patrik ,  BERNDTSSON, Andreas

IPC: H01P3/08 ,  H05K1/14 ,  H01R9/00

CPC classification number: H01P3/085 ,  H05K1/0237 ,  H05K1/144 ,  H05K3/325 ,  H05K3/4046 ,  H05K2201/0379 ,  H05K2201/043 ,  H05K2201/10303 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: The present invention relates to a stripline arrangement (10’) comprising a number of stripline layers each comprising a laminate layer (1A, 1B) and conducting layers (2A, 2B, 3A, 3B) provided on each of said laminate layers (1A, 1B), said conducting layers (2A, 2B, 3A, 3B) each comprising a conductive pattern, RF signal (microwave) input and output ports respectively, and an interconnecting arrangement (5) for interconnecting said layers. At least two of said stripline layers are arranged such that a given overlapping zone (L’) is provided between each other facing conducting layers (2A, 2B) of said striplines layers, said interconnecting arrangement (5) comprising a bonding arrangement provided between adjacent and one another facing and overlapping conducting layers (2A, 2B). Connectors (4A, 4B) are provided substantially perpendicularly with respect to an extension plane of the respective stripline layers and crossing said laminate layers (1A, 1B) and conducting layers for, in said overlapping zone, providing contact between the adjacent conducting layers of adjacent stripline layers.

公开(公告)号：EP1269807B1

公开(公告)日：2006-01-18

申请号：EP01914939.2

申请日：2001-03-30

Applicant: Dyconex AG

Inventor： SCHMIDT, Walter

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K3/4084 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/0195 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

Abstract: The invention comprises a method for manufacturing electrical connecting elements or semifinished products. Microvias are formed in a dielectric substrate layer by piercing a substrate layer (1) through a first conducting layer (3), which essentially covers an entire side of the substrate. The perforation depth (d) is at least equal to the total thickness of the substrate (1) and the first conducting layer (3). The conductor material of the first conducting layer (3) during the piercing step is deformed so that it partially covers the wall of the hole fabricated by the piercing process. The little remaining distance between the conductor material and the opposite side of the substrate layer can easily be bridged by plating the side of the first conducting layer (3) with additional conductor material. In this way, a reliable via contact is formed.

公开(公告)号：EP1269808A1

公开(公告)日：2003-01-02

申请号：EP01916828.5

申请日：2001-03-30

Applicant: DYCONEX PATENTE AG

Inventor： SCHMIDT, Walter

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer (11,11') and a prefabricated product (1) are placed between two perforation dies (21,23) or a support and a perforation die. The prefabricated product (1) is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die (21,22), perforation tips of the perforation dies forming microvias for contacting the structures. A surface of the dielectric layer (11,11') or the prefabricated product (1) is configurated or coated to in a manner that the prefabricated product (1) and the dielectric layer (11,11') stick to each other after the pressure has been applied.

公开(公告)号：EP0668713A1

公开(公告)日：1995-08-23

申请号：EP95200340.8

申请日：1995-02-13

Applicant: HOLLANDSE SIGNAALAPPARATEN B.V.

Inventor： Hummelink, Edwin Johannes Hendrikus

IPC: H05K3/42 ,  H01P11/00

CPC classification number: H01P11/00 ,  H05K1/0219 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/09718 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/171 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Method for manufacturing a multilayer microwave board in one operation. Individually etched layers (2,3,5,6) of a laminate (1,4,10,12), such as duroid, are bonded to form a package and drilled after which the resulting holes (9) are plated. Next, the superfluous connections (15,16) are removed by drilling during which process each stripline-coax transition buried in the package is tuned by a correct selection of the drill diameter and the hole depth.

Abstract translation: 用于在一次操作中制造多层微波板的方法。 的层压体（1,4,10,12）的单独蚀刻层（2,3,5,6-）：如DUROID，结合形成一个包，并钻出afterwhich所得的孔（9）的镀敷。 接着，将多余的连接（15,16）是通过在此期间，过程掩埋包中的每个带状线同轴过渡通过钻头直径的正确选择和孔深度调谐钻孔移除。

公开(公告)号：EP0248566A3

公开(公告)日：1990-01-31

申请号：EP87304510.8

申请日：1987-05-21

Applicant: AT&T Corp.

Inventor： LoVasco, Francis ,  Oien, Michael Ackman

IPC: H01L21/58 ,  H01L21/60 ,  H05K3/34

CPC classification number: H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/81024 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/035 ,  H05K2201/0379 ,  H05K2201/09909 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/043 ,  H05K2203/0465 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/29099

Abstract: A solder joint assembly technique applies controlled volumes of solder to pads of both package and substrate (31, 32). The two units are positioned adjacent each other with the pads and solder deposits mechanically maintained in registration with each other (34, 35). The assembly is reflowed and the final separation between package and substrate at which the resulting solder joint solidifies is mechanically controlled in order to control a geometry of the resultant solidified joint (36, 37). The solder volume deposits may assume various forms including spherical bumps and solder paste deposits.

公开(公告)号：EP2907191A4

公开(公告)日：2016-04-13

申请号：EP13847868

申请日：2013-08-08

Applicant: RAYTHEON CO

Inventor： BROWN ANDREW K ,  OBERT THOMAS L ,  SOTELO MICHAEL J ,  GRITTERS DARIN M ,  BROWN KENNETH W

IPC: H01P1/162

CPC classification number: H05K1/167 ,  H05K1/0234 ,  H05K1/0242 ,  H05K3/06 ,  H05K2201/0379 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/09781

公开(公告)号：EP2326155A4

公开(公告)日：2012-01-11

申请号：EP09815968

申请日：2009-06-02

Applicant: SHARP KK

Inventor： SHIOTA MOTOJI ,  NAGAOKA GEN ,  UMEKAWA ICHIRO ,  HIDA YASUHIRO ,  SHIMIZU YUKIO

IPC: H05K3/32 ,  G02F1/1345 ,  H01L21/60 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K3/323 ,  G02F1/13452 ,  H01L2224/73204 ,  H01L2924/07811 ,  H05K1/0231 ,  H05K3/284 ,  H05K3/361 ,  H05K2201/0379 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

公开(公告)号：EP2146374A1

公开(公告)日：2010-01-20

申请号：EP09163681.1

申请日：2009-06-24

Applicant: Thales Holdings UK Plc

Inventor： Loiselet, Emmanuel ,  Wills, Phil

IPC: H01L23/367 ,  H01L23/433 ,  H05K1/02

CPC classification number: H01L23/433 ,  H01L23/367 ,  H01L23/473 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H05K1/0203 ,  H05K3/0061 ,  H05K2201/0379 ,  H05K2201/09054 ,  H05K2201/10734 ,  H05K2203/167 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An assembly comprising a first printed circuit board, PCB (5), with a ball grid array, BGA (6), on its underside, a second PCB (8) facing the first PCB and having at least one through-hole (11) between its top and bottom surfaces, its top surface printed with a circuit pattern bonded to the BGA, a heat sink layer (9) facing the bottom surface of the second PCB and having at least one thermally-conductive pin projecting normally into the through-hole (11) or a respective one of the through-holes in the second PCB, and, for each pin, a thermally-conductive stud of the same cross-section as the pin, bonded to the BGA (6) and disposed within the through-hole (11) between the pin and the first PCB in thermal contact with the pin.

Abstract translation: 一种组件，其包括在其下侧上具有球栅阵列BGA（6）的第一印刷电路板PCB（5），面向第一PCB且具有至少一个通孔（11）的第二PCB（8） 在其顶面和底面之间，其上表面印刷有结合到BGA的电路图案，面向第二PCB的底面的散热层（9），并具有至少一个导热销， （11）或第二PCB中的相应一个通孔，并且对于每个管脚，具有与管脚相同横截面的导热管柱，接合到BGA（6）并布置在 所述引脚与所述第一PCB之间的通孔（11）与所述引脚热接触。