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    High performance metal cone contact
    64.
    发明公开
    High performance metal cone contact 失效
    Hochleistungsfähigerkonischer Metallkontakt。

    公开(公告)号：EP0480194A2

    公开(公告)日：1992-04-15

    申请号：EP91115460.7

    申请日：1991-09-12

    Applicant: International Business Machines Corporation

    Inventor： Datta, Madhav ,  King, David E. ,  Knight, Alan D. ,  Sambucetti, Carlos J.

    IPC: H05K1/00 ,  H05K3/00 ,  H01R23/72 ,  H01R13/24 ,  C23F1/02 ,  H05K3/38

    CPC classification number: H05K3/07 ,  H01L2924/0002 ,  H01R13/03 ,  H01R13/22 ,  H01R43/16 ,  H05K3/064 ,  H05K3/383 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2203/0369 ,  Y10T29/49222 ,  H01L2924/00

    Abstract: An electrical interconnection, which includes a method for fabricating the device, is disclosed. The interconnection comprises two contact surfaces, on at least one of which is disposed at least one solid metal conical projection in predetermined dimension and location. Rather than necessarily being permanently cojoined, the contact surfaces are attachable and detachable when desired. The conical projections on one contact surface make ohmic contact, either by wiping with an intermeshing like structure on a second contact surface or by contacting a second contact surface which is a substantially flat contact pad. An interconnection, in this invention, is the combination of at least one contact having individual conical projections and another contact, optionally having individual conical projections. The conical projections are formed in metal by electrochemical machining in neutral salt solution, optionally in a continuous foil. The conical projections are also optionally formed on the head of a contact pin.

    Abstract translation: 公开了一种包括制造该装置的方法的电互连。 互连包括两个接触表面，其中至少一个接触表面设置有至少一个预定尺寸和位置的固体金属锥形突起。 不是必须永久地共同接合，所以当需要时，接触表面是可附接的和可拆卸的。 一个接触表面上的锥形突起通过在第二接触表面上以相互啮合的结构擦拭或者通过接触作为基本上平坦的接触垫的第二接触表面来进行欧姆接触。 在本发明中的互连是至少一个具有单个锥形突起的接触件和另一接触件的组合，可选地具有各自的锥形突出部。 锥形凸起通过在中性盐溶液中的电化学机械加工形成金属，任选地在连续的箔中。 锥形突起也可选地形成在接触销的头部上。

    Manufacturing method for a multilayer wiring board
    65.
    发明公开
    Manufacturing method for a multilayer wiring board 失效
    Verfahren zur Herstellung von gedruckten Mehrschicht-Leiterplatten。

    公开(公告)号：EP0459665A1

    公开(公告)日：1991-12-04

    申请号：EP91304414.5

    申请日：1991-05-16

    Applicant: International Business Machines Corporation

    Inventor： Murakami, Takahiro

    IPC: H05K3/46

    CPC classification number: H05K3/243 ,  H01L2224/81191 ,  H05K3/064 ,  H05K3/4647 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0505 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49156

    Abstract: A method of manufacturing a multilayer wiring board is provided in which interlayer connection is made between a first electric circuit and a second electric circuit, both electric circuits being formed on a substrate. Firstly a metal layer is applied onto the substrate and a photoresist is deposited onto the metal layer. Then the photoresist is partially removed to produce a resist hole and the remaining photoresist is selectively exposed in accordance with the desired pattern for the first electric circuit. Next a conductive pillar is formed in the resist hole, followed by the removal of the exposed remaining photoresist to reveal corresponding regions of the metal layer below. These regions of the metal layer are then etched to partly expose the substrate and to form said first electric circuit. All remaining photoresist is removed and an insulation layer is deposited on the first electric circuit, the exposed substrate, and the conductive pillar, such that only one end of the conductive pillar remains exposed. Then a second metal layer is deposited on the surface of the insulation layer and the exposed end of the conductive pillar to form the second electric layer cirrcuit.
    The above method facilitates accurate alignment between the first wiring circuit and the conductive pillar and hence enables high density circuits to be achieved. It also reduces the number of manufacturing steps required since the same photoresist layer is used in both the resist hole formation step and the circuit pattern formation step.

    Abstract translation: 提供一种制造多层布线板的方法，其中在第一电路和第二电路之间进行层间连接，两个电路都形成在基板上。 首先将金属层施加到基底上，并将光致抗蚀剂沉积到金属层上。 然后部分去除光致抗蚀剂以产生抗蚀剂孔，并且根据第一电路的期望图案选择性地暴露剩余的光致抗蚀剂。 接下来，在抗蚀孔中形成导电柱，然后除去暴露的剩余光致抗蚀剂，以露出下面金属层的相应区域。 然后蚀刻金属层的这些区域以部分地暴露衬底并形成所述第一电路。 去除所有剩余的光致抗蚀剂，并且在第一电路，暴露的衬底和导电柱上沉积绝缘层，使得只有导电柱的一端保持露出。 然后在绝缘层的表面和导电柱的暴露端沉积第二金属层以形成第二电层电感。 上述方法有助于第一布线电路和导电柱之间的精确对准，从而实现高密度电路。 由于在抗蚀剂孔形成步骤和电路图案形成步骤中都使用相同的光致抗蚀剂层，所以也减少了所需的制造步骤的数量。

    Method of forming of an integrated circuit chip packaging structure
    67.
    发明公开
    Method of forming of an integrated circuit chip packaging structure 失效
    Packensstrukturfüreinen integrierten Schaltungschip。

    公开(公告)号：EP0411165A1

    公开(公告)日：1991-02-06

    申请号：EP89113765.5

    申请日：1989-07-26

    Applicant: International Business Machines Corporation

    Inventor： Gansauge, Peter, Dr. ,  Kreuter, Volker, Dipl.-Ing. ,  Schettler, Helmut, Dipl.-Ing.

    IPC: H01L21/48

    CPC classification number: H01L21/4846 ,  H01L21/4853 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H05K1/113 ,  H05K3/061 ,  H05K3/243 ,  H05K3/388 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0574 ,  H05K2203/0585

    Abstract: An integrated circuit chip packaging structure com­prising a substrate (10), preferably a semiconductor base substrate, a conductive layer (20) on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls (36) and gold bumps (34) connected to said conductive layer in said regions of said conductive layer, and a solder stop layer (22) on said conductive layer at least around said solder balls. The conductive layer further comprises wiring lines (30). Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus one metallization layer is pre­vented. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus packaging of VLSI circuits is improved.

    Abstract translation: 一种集成电路芯片封装结构，包括在形成与基板的金属化层的连接的区域中的衬底（10），优选半导体基底衬底，在所述衬底上的导电层（20），焊球（36）和金凸块 34），其连接到所述导电层的所述区域中的所述导电层，以及在所述导电层上至少围绕所述焊球的焊料停止层（22）。 导电层还包括布线（30）。 此外，公开了一种形成结构的方法，其仅使用两个掩模来提供用于将基板连接到集成电路和其它基板或印刷电路板和布线的端子。 因此，防止了一个金属化层。 该方法适用于200 mm晶圆，并允许在同一基板上使用两种不同的封装技术（C-4和TAB或引线键合）。 因此，VLSI电路的封装得到改善。

    Excimer induced topography of flexible interconnect structures
    68.
    发明公开
    Excimer induced topography of flexible interconnect structures 失效
    准分子诱导剂灵活的Zusammenschaltungsstruktur。

    公开(公告)号：EP0403851A2

    公开(公告)日：1990-12-27

    申请号：EP90110389.5

    申请日：1990-05-31

    Applicant: Hughes Aircraft Company

    Inventor： Schreiber, Christopher M.

    IPC: H05K3/40 ,  H05K3/00 ,  H01L21/48 ,  H01R13/24

    CPC classification number: H05K3/0035 ,  H05K1/0393 ,  H05K3/281 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0577 ,  H05K2203/107 ,  H05K2203/1383 ,  Y10T29/49165

    Abstract: A raised metal connection feature (29) is created by forming a conductive pad (17) on a flexible substrate (11) and applying a flexible dielectric insulator (19) and photoresist layer (21) over the conductive pad (17). An excimer laser (25) is used to ablate a via (27) through the dielectric insulator (19) and photoresist (21) to the conductive pad (17). Gold or other metal is then plated up in the via (17), and the photoresist (21) is removed, leaving a metal feature (29) extending above the dielectric insulator (19).

    Abstract translation: 通过在柔性基板（11）上形成导电垫（17）并在导电垫（17）上方施加柔性电介质绝缘体（19）和光致抗蚀剂层（21）来产生凸起的金属连接特征（29）。 使用准分子激光器（25）将通过电介质绝缘体（19）和光致抗蚀剂（21）的通孔（27）烧蚀到导电焊盘（17）。 然后将金或其他金属镀在通孔（17）中，并且去除光致抗蚀剂（21），留下在电介质绝缘体（19）上方延伸的金属特征（29）。

    Verfahren zur Herstellung von mit Kontaktflächen versehenen Gedruckten Schaltungen
    69.
    发明公开
    Verfahren zur Herstellung von mit Kontaktflächen versehenen Gedruckten Schaltungen 失效
    一种用于制备设置有印刷电路板的接触表面处理。

    公开(公告)号：EP0374483A2

    公开(公告)日：1990-06-27

    申请号：EP89121279.7

    申请日：1989-11-17

    Applicant: Schoeller & Co. Elektronik GmbH ,  Degussa Aktiengesellschaft

    Inventor： Ritz, Klaus, Dr.

    IPC: H05K3/40 ,  H05K3/10

    CPC classification number: H05K3/4007 ,  H05K3/022 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0382

    Abstract: Zur Herstellung von mit Kontaktflächen versehenen Gedruckten Schaltungen werden Kupferfolien gegen eine mit erhabenen Flächen in einem vorgegebenen Muster versehene Schablone gepresst und das Innere der in den Kupferfolien entstandenen Prägeabdrücke mit einem aushärtenden Material ausgefüllt. Nach dem Vorpressen mit Prepregs werden aus diesen Vorlaminaten Gedruckte Schaltungen erzeugt. Die Kupferfolien müssen hierbei eine Bruchdehnung > 10% und eine Dicke von 10 bis 100 µm aufweisen.

    Abstract translation: 用于制造设置有接触区域印刷电路，铜膜被压在以预定的图案设置有凸起区域的模板，并在铜膜中产生的印象深刻印记的内部填充有凝固材料。 与预浸料坯压制预后，印刷电路由合成预层压材料制造。 铜薄膜必须具有这里的> 10％的断裂张力，厚度为10至100微米。

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