公开(公告)号：EP0935256B1

公开(公告)日：2002-05-08

申请号：EP99105448.7

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke ,  Yamazaki, Hirokazu ,  Watanabe, Hisayoshi ,  Kasa, Yasushi

IPC: G11C29/00 ,  H01L21/02

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

公开(公告)号：EP0929900B1

公开(公告)日：2001-11-28

申请号：EP97945360.2

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WENDELL, Dennis, L.

IPC: G11C29/00 ,  G11C5/14

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.

公开(公告)号：EP0933785A1

公开(公告)日：1999-08-04

申请号：EP99105456.0

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke Fujitsu Limited ,  Yamazaki, Hirokazu Fujitsu Limited ,  Watanabe, Hisayoshi Fujitsu Limited ,  Kasa, Yasushi Fujitsu Limited

IPC: G11C29/00 ,  G11C5/14 ,  G11C11/407

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: The semiconductor device has a normal power supply and an independent power supply provided independently of the normal power supply, either of which is selectable as a power supply for an output circuit. The device comprises a power supply selecting circuit (6) that outputs a signal for selecting one of the power supplies in accordance with the level of an externally applied signal.

公开(公告)号：EP0929939A1

公开(公告)日：1999-07-21

申请号：EP97945362.0

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PARTOVI, Hamid ,  HOLST, John, Christian ,  BEN-MEIR, Amos

IPC: G06F12 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed Pulse Control (STPC) circuit is integrated onto an integrated circuit chip along with the circuit structures that are timed using timing structures that are adjusted using STPC. The STPC is also advantageously used to modify the duty cycle of clocks, determine critical timing paths so that overall circuit speed is optimized, and adjusting dynamic circuit timing so that inoperable circuits become useful.

公开(公告)号：EP0929898A1

公开(公告)日：1999-07-21

申请号：EP97945064.0

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WENDELL, Dennis, Lee ,  HOLST, John, Christian

IPC: G06F12 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995 ,  Y02D10/13

Abstract: A highly suitable power conservation technique involves extending multiple word lines over a memory array row and connecting a portion of the memory cells of the memory array row to each of the word lines. Power is supplied only to the portion of the memory cells that is accessed, eliminating the static power consumption of the non-accessed memory cells. By connecting multiple word lines to select a portion of a memory row, a column address of the memory is mapped into a row decode space. Multiple metal layers in a complex integrated circuit may be exploited to form cache block select lines using multiple word lines per cell row. A storage includes a plurality of storage cells arranged in an array of rows and columns, a plurality of bit lines connecting the array of storage cells into columns, and a plurality of word lines connecting the array of storage cells into rows. The plurality of word lines include multiple word lines for a single row of the plurality of rows so that multiple portions of the storage cells in the single row are addressed by corresponding multiple word lines.

公开(公告)号：EP0929896A1

公开(公告)日：1999-07-21

申请号：EP97944574.0

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian

IPC: G06F12 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C29/026 ,  G11C7/00 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A memory includes a data bit line and a reference bit line. Word lines in the memory are connected to the bit lines by transistors. The transistors on data bit lines and the reference bit lines are substantially the same size. The capacitances on the data bit lines are substantially the same as the capacitances on the reference bit lines. When the word line is activated, the bit lines express a steady-state voltage that is a function of the resistance of the bit lines. In one example, the data bit lines have a resistance (R) and the reference bit lines have half the resistance (R2). The same current is sourced to the data bit lines and the reference bit lines so that the steady-state voltage of the data bit line differs from the steady-state voltage of the reference bit line by a factor equal to the ratio of the resistances. The resistors (R and R2) perform two functions, the resistors clamp level of the bit lines that are being discharged to stop the displacement current. The data bit lines are sensed differentially with respect to the reference.

公开(公告)号：EP0836196A3

公开(公告)日：1999-06-09

申请号：EP97117402.4

申请日：1997-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： San, Kemal T. ,  Kaya, Cetin ,  Mehrad, Freidoon

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3409 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).

公开(公告)号：EP0718850B1

公开(公告)日：1998-02-25

申请号：EP95402815.5

申请日：1995-12-14

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： Mirabel, Jean-Michel ,  Yero, Emilio

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C16/04 ,  G11C2029/5006

公开(公告)号：EP0698273A1

公开(公告)日：1996-02-28

申请号：EP95907132.0

申请日：1995-02-15

Applicant: Philips Electronics N.V.

Inventor： SACHDEV, Manoj

IPC: G01R31 ,  G11C8 ,  G11C29

CPC classification number: G11C29/50 ,  G11C8/04 ,  G11C8/12 ,  G11C11/41 ,  G11C29/34 ,  G11C2029/5006

Abstract: An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises IDDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for IDDQ test purposes only.

公开(公告)号：EP0594920A1

公开(公告)日：1994-05-04

申请号：EP92830589.5

申请日：1992-10-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Cappelletti, Paolo Giuseppe ,  Ravazzi, Leonardo

IPC: G11C29/00 ,  H01L21/66

CPC classification number: G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method employing a test structure (10) identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically (13-15, 17, 18, 19-21) parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.

Abstract translation: 使用与要确定其栅极氧化物质量的存储器阵列相同的测试结构（10）的方法，除了电池彼此平行的电连接（13-15,17,18,19-21）的事实之外 。 测试结构被电应力地从缺陷栅极 - 氧化物电池的浮动栅极提取电子，并因此改变电池的特性，同时保持无缺陷电池的电荷不变。 以这种方式，只有有缺陷的单元的阈值被改变。 然后将亚阈值电压施加到测试结构，并且测量与结构中存在至少一个有缺陷单元有关的通过单元的漏极电流。 电流 - 电压特性的测量和分析提供了确定缺陷单元的数量。 该方法适用于EPROM，EEPROM和闪存EEPROM存储器的栅氧化物的在线质量控制。