公开(公告)号：EP0497948B1

公开(公告)日：1995-05-03

申请号：EP91914937.7

申请日：1991-08-23

Applicant: THOMSON-CSF

Inventor： LEROY, Michel ,  VAL, Christian

IPC: H05K3/28

CPC classification number: H05K3/284 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0715 ,  H05K2201/09872 ,  H05K2203/1322

Abstract: In one embodiment, the discreet or integrated electronic components are each encapsulated in a package which may, for example, be plastic. The packages are then mounted on a printed circuit board made, for example, from epoxy. The assembled components and board are covered with a first relatively thick layer of an organic compound providing a levelling function, followed by a second layer consisting, for example, of a mineral metallic compound which serves to hermetically seal the assembly.

公开(公告)号：EP0451500A3

公开(公告)日：1995-02-08

申请号：EP91103285.2

申请日：1991-03-05

Applicant: International Business Machines Corporation

Inventor： Lauffer, John Matthew ,  Schumacher, Richard Anthony

IPC: H05K3/46 ,  H01L23/538 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  Y10S257/916 ,  Y10T29/435

Abstract: Disclosed is a multilayer circuit package (101) having a buried thin film capacitor (141). The circuit packages includes at least a power core (111a), a ground core (111b), a first signal core (121), a second signal core (131), and the integral, buried, thin film capacitor. The integral, buried, thin film capacitor (141) serves to capacitively couple the first and second signal cores. Structurally, the first signal core includes at least one first wire (123) that terminates in at least one first electrode (125), while the second signal core includes at least one second wire (133) that terminates in at least one second electrode (135). At least a portion of the first electrode overlays at least a portion of the second electrode and is separated therefrom by a thin film of a dielectric material (151). The first electrode, the second electrode, and the thin film of dielectric material define the integral buried capacitor. The thin film capacitor is prepared by thin film methods, with epitaxial deposition of the dielectric.

Abstract translation: 公开了一种具有埋入式薄膜电容器（141）的多层电路封装（101）。 电路封装包括至少一个功率芯（111a），接地芯（111b），第一信号芯（121），第二信号芯（131）和整体埋入式薄膜电容器。 整体埋入式薄膜电容器（141）用于电容耦合第一和第二信号核心。 结构上，第一信号芯包括终止于至少一个第一电极（125）的至少一个第一导线（123），而第二信号芯包括终止于至少一个第二电极（125）的至少一个第二导线（133） 135）。 第一电极的至少一部分覆盖第二电极的至少一部分并且通过介电材料薄膜（151）与第二电极分开。 第一电极，第二电极和介电材料薄膜限定了整体埋入式电容器。 薄膜电容器通过薄膜方法制备，外延沉积电介质。

公开(公告)号：EP0409668B1

公开(公告)日：1995-01-25

申请号：EP90308039.8

申请日：1990-07-23

Applicant: OMRON CORPORATION

Inventor： Kawai, Wakahiro ,  Kita, Motohiro ,  Matsuda, Katsumi

IPC: H05K1/16 ,  H05K3/20

CPC classification number: H05K1/162 ,  H05K1/167 ,  H05K3/06 ,  H05K3/20 ,  H05K3/429 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763 ,  H05K2203/0152 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/072

公开(公告)号：EP0526656A4

公开(公告)日：1993-04-14

申请号：EP92905294

申请日：1992-02-24

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： HARADA, KEIZO, ITAMI WORKS OF SUMITOMO EL.IND.LTD. ,  TAKIKAWA, TAKATOSHI, ITAMI WORKS OF SUMITOMO EL. ,  MAEDA, TAKAO, ITAMI WORKS OF SUMITOMO EL.IND.LTD. ,  BAN, SHUNSUKE, ITAMI WORKS OF SUMITOMO EL.IND. ,  YAMANAKA, SHOSAKU,

IPC: H01L23/14 ,  H01L23/495 ,  H01L23/498 ,  H05K1/05 ,  H01L23/12

CPC classification number: H05K1/053 ,  H01L23/142 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H05K2201/0179 ,  H05K2201/0317 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A wiring board having a reliable and cheaply fabricated wiring circuit which can be easily formed in a fine form enabling the semiconductor devices to be more densely integrated in further reduced thickness, reduced size and at reduced cost, the wiring board capable of being sealed in a plastic package. A thin dielectric film (2) is formed on the surface of a metal plate (1), and a semiconductor element (8) is mounted on the surface of the dielectric (2) or on the exposed surface of the metal plate (1). On the dielectric (2), thin multilayered wiring films (3), (4) and (5) are formed by sequential vapor deposition of a conductor layer of aluminum; an adhesive layer of chromium, or titanium or a laminate thereof; a diffused barrier layer of nickel, or copper or laminate thereof; and a corrosion-preventing/wire-bonding layer of gold. The wiring may comprise an adhesive layer of any one of chromium, aluminum or titanium, or a laminate thereof, a conductor layer of copper and a gold layer that are formed in the order mentioned, or may comprise a conductor layer of aluminum, a barrier layer of nickel and a gold layer formed in the order mentioned. The thin-film wiring can be finely formed with ease enabling the wiring conductors to be highly densely fabricated. Moreover, the wiring composed of aluminum or copper can be cheaply formed.

Abstract translation: 一种具有可靠且廉价制造的布线电路的布线板，其可以容易地以精细的形式形成，使得半导体器件能够以更小的厚度，更小的尺寸和更低的成本更加密集地集成在一起，能够被密封在 塑料包装。 在金属板（1）的表面上形成有薄的电介质膜（2），并且在电介质（2）的表面上或金属板（1）的暴露表面上安装半导体元件（8） 。 在电介质（2）上，通过铝的导体层的顺序气相沉积形成薄的多层布线膜（3），（4）和（5） 铬或钛的粘合剂层或其层压体; 镍的扩​​散阻挡层或铜或其层压体; 和金的防腐蚀/引线接合层。 布线可以包括铬，铝或钛中的任何一种或其层压体的粘合剂层，按所述顺序形成的铜和金层的导体层，或者可以包括铝的导体层，阻挡层 镍层和金层按所述顺序形成。 可以容易地形成薄膜布线，使得布线导体可以被高密度地制造。 此外，可以廉价地形成由铝或铜构成的布线。

公开(公告)号：EP0523479A2

公开(公告)日：1993-01-20

申请号：EP92111335.3

申请日：1992-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brauer, John M. ,  Christie, Frederich R. ,  Lawrence, William R. ,  Mehta, Ashit A. ,  Reid, Jonathan D. ,  Summa, William J.

IPC: H05K3/44 ,  H05K3/46 ,  H05K1/05

CPC classification number: H05K3/445 ,  H01L23/142 ,  H01L2924/0002 ,  H05K1/056 ,  H05K3/388 ,  H05K3/389 ,  H05K3/4076 ,  H05K3/426 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2203/135 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a multilayer electronic circuit package. The multilayer circuit package has at least one layer that is a circuitized, polymer encapsulated metal core. According to the method of the invention a metal foil is provided for the metal core of the layer. This metal core foil may be provided as a single unit or in a continuous, roll to roll, process. The vias and through holes are drilled, etched, or punched through the metal foil. An adhesion promoter is then applied to the perforate metal foil for subsequent adhesion of polymer to the foil. The dielectric polymer is then applied to the perforate metal foil core by vapor depositing, chemical vapor depositing, spraying, or electro-phoretically depositing, a thermally processable dielectric polymer or precursor thereof onto exposed surfaces of the perforate metal foil including the walls of the through holes and vias. The dielectric polymer or precursor thereof is then thermally processed to form a conformal dielectric, polymeric coating on surfaces of the perforate metal foil, including the interior surfaces of the vias and through holes. This dielectric, polymeric coating may then be circuitized, and coated with an adhesive for lamination to the next adjacent layer. After lamination, one or more chips are attached to the completed package.

Abstract translation: 公开了一种制造多层电子电路封装的方法。 多层电路封装具有至少一层是电路化的聚合物封装的金属芯。 根据本发明的方法，为该层的金属芯提供金属箔。 该金属芯箔可以设置为单个单元或以连续的卷对卷方式提供。 通过金属箔钻孔，蚀刻或冲压通孔和通孔。 然后将粘合促进剂施加到穿孔金属箔上，以便随后将聚合物粘附到箔上。 然后将电介质聚合物通过气相沉积，化学气相沉积，喷涂或电沉积，将热可加热的介电聚合物或其前体涂覆到穿孔金属箔的暴露的表面上，包括通孔的壁 孔和通孔。 然后将介电聚合物或其前体进行热处理以在穿孔金属箔的表面上形成共形电介质聚合物涂层，包括通孔和通孔的内表面。 然后可以将该介电聚合物涂层电路化，并用粘合剂涂覆以层压到下一相邻层。 在层压之后，将一个或多个芯片附接到完成的封装。

公开(公告)号：EP0498258A1

公开(公告)日：1992-08-12

申请号：EP92101294.4

申请日：1992-01-27

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Birkle, Siegfried, Dr. ,  Kammermaier, Johann, Dr. ,  Rittmayer, Gerhard, Dr. ,  Schulte, Rolf Winfried

IPC: H05K3/46

CPC classification number: H05K3/0041 ,  H05K3/108 ,  H05K3/381 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09563 ,  H05K2203/095

Abstract: Bei einem Verfahren zur Herstellung von Mehrlagenverdrahtungselementen, insbesondere auf Leiterplatten, wird zunächst das Grundsubstrat metallisiert, darauf eine Photolackschicht aufgebracht, photolithographisch eine Leitungsbahnstruktur erzeugt und diese metallisch verstärkt und der restliche Photolack sowie das darunter befindliche Metall werden entfernt. Dann wird die gesamte Struktur mit einer planarisierenden Plasmapolymerisatschicht auf CF-Basis oder einer Schicht aus amorphem wasserstoffhaltigem Kohlenstoff (a-C:H) abgedeckt, die Oberfläche dieser Schicht mittels eines Sauerstoffplasmas aktiviert und darauf zunächst eine dünne Metallschicht und anschließend ein siliciumhaltiger Photolack aufgebracht. Nachfolgend werden Durchkontaktierungsstellen zu den Kontaktflächen hergestellt, in der Lackschicht wird photolithographisch eine Leitungsbahnstruktur erzeugt, Kontaktflächen und Leitungsbahnstruktur werden metallisch verstärkt und der restliche Photolack sowie das darunter befindliche Metall werden entfernt.

Abstract translation: 在制造多层布线元件的过程中，特别是在印刷电路板上，首先对基底基板进行金属化，在其上沉积光致抗蚀剂层，光刻地制造导体轨道结构，后者制成较厚的金属并且光刻胶的其余部分 并且其下面的金属被去除。 然后用基于CF或非晶态含氢碳（aC：H）层的可平面等离子体聚合物层涂覆整个结构，所述层的表面借助氧等离子体活化，薄金属层为 首先沉积在其上，随后是含硅光致抗蚀剂。 然后产生与接触区域的直接接触点，在抗蚀剂层中光刻地形成导体轨道电路，使金属上的接触区域和导体轨道结构变得更厚，并且除去其余的光致抗蚀剂和其下面的金属。

公开(公告)号：EP0099544A1

公开(公告)日：1984-02-01

申请号：EP83106871.3

申请日：1983-07-13

Applicant: International Business Machines Corporation

Inventor： Schaible, Paul Martin ,  Suierveld, John

IPC: H01L21/48

CPC classification number: H05K3/4647 ,  H01L21/486 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01012 ,  H01L2924/09701 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K3/061 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2203/0369 ,  H05K2203/0733

Abstract: A multilevel metallurgy is formed on a dielectric body, particularly a multilayer ceramic (MLC) body (10). The interconnection lines (22) and via studs (26) are formed as an integral structure from a blanket metal layer thus eliminating the interface beween the via pad and via stud. A second level of interconnections (25) can be formed on top of said first interconnection level.

公开(公告)号：EP0057085A2

公开(公告)日：1982-08-04

申请号：EP82300306.6

申请日：1982-01-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Nagashima, Kenji ,  Matsumoto, Hiroshi ,  Tanaka, Masataka ,  Oodaira, Hirosi ,  Iwase, Nobuo

IPC: H01L21/48 ,  H01L25/16 ,  H01L49/02 ,  H01L23/14

CPC classification number: H05K3/22 ,  H01L21/4846 ,  H01L23/142 ,  H01L23/3735 ,  H01L25/16 ,  H01L2224/48227 ,  H05K1/053 ,  H05K2201/0116 ,  H05K2201/0179 ,  H05K2203/1147 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A method for manufacturing a hybrid integrated circuit device comprising a step of forming an Al 2 O 3 layer (22) on a metal substrate (21), a step of forming on the Al 2 O 3 layer (22) a resist layer (23) having a pattern opposite to that of a copper layer (24) which will be formed on the Al 2 O 3 layer (22) by a later step, a step of forming the copper layer (24) on the Af 2 0 3 layer (22) using the resist layer (23) as a mask, a step of impregnating thermosetting material into both the Al 2 O 3 layer (22) and the copper layer (24), and a step of providing at least one semiconductor element (26, 27, 28) on the copper layer (24).

公开(公告)号：EP0023324A1

公开(公告)日：1981-02-04

申请号：EP80104211.0

申请日：1980-07-18

Applicant: International Business Machines Corporation

Inventor： Clark, Roger James ,  Kennison, Robert Ellis

IPC: B05D1/32 ,  H05K13/00 ,  H05K3/28

CPC classification number: B05D1/60 ,  B05D1/327 ,  H05K3/284 ,  H05K2201/0179 ,  H05K2201/09872 ,  H05K2201/10303 ,  H05K2203/304

Abstract: A method of masking a workpiece (21) to prevent the adhesion of a deposited tightly adhering conformal coating (28) formed from the condensation of a vaporous diradical such as paraxylylene on selected portions of the workpiece. The process requires the covering of those areas of the workpiece to which adhesion is not desired with a non-polymerizing hydrocarbon (26) and placing the covered area in close contact with an open cellular material (27) containing a predominance of interconnecting cells which provide a large surface area for condensation of the unwanted condensate of the diradical, exposing the workpiece (21) to the vaporous diradical, removing the workpiece (21) from the open cellular material (27) and immersing the workpiece in a solvent for swelling and dissolving the hydrocarbon (26) covering.

Abstract translation: 一种掩蔽工件（21）以防止由气相双基（例如对二甲苯）冷凝形成的沉积紧密粘合的保形涂层（28）粘附在工件的选定部分上的方法。 该方法需要用非聚合烃（26）覆盖不需要粘附的工件的那些区域，并将覆盖区域与包含主要互连电池的开放的多孔材料（27）紧密接触， 用于冷凝双向不需要的冷凝物的大的表面积，将工件（21）暴露于气态双基底，从打开的多孔材料（27）移除工件（21）并将工件浸入用于溶胀和溶解的溶剂中 碳氢化合物（26）覆盖。

公开(公告)号：EP2109124B1

公开(公告)日：2017-03-29

申请号：EP08703922.8

申请日：2008-01-25

Applicant: Showa Denko K.K.

Inventor： SHIRAKAWA, Akihiko ,  MITSUMOTO, Ryuichi ,  TOKITA, Koji

IPC: H01G4/20 ,  H01G4/10 ,  H01G4/12 ,  H01G9/052 ,  H01G4/33 ,  H05K1/16 ,  H01G9/07 ,  H01G9/00

CPC classification number: H01G4/33 ,  H01G4/1218 ,  H01G4/20 ,  H01G9/0032 ,  H01G9/052 ,  H01G9/07 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/0315 ,  Y10T156/10 ,  Y10T428/266

Abstract: The capacitor material of the present invention is comprised by laminating a titanium dioxide layer and a titanate compound layer having perovskite crystals.

Abstract translation: 本发明的电容器材料通过层叠二氧化钛层和具有钙钛矿型结晶的钛酸化合物层构成。