公开(公告)号：EP0549791B1

公开(公告)日：1997-07-16

申请号：EP91909937.4

申请日：1991-04-01

Applicant: Aktsionernoe obschestvo otkrytogo tipa VNIIETO

Inventor： ADASKO, Vladimir Iosifovich ,  VARDENBURG, Arnold Kurtovich ,  EMELYANOV, Alexandr Lvovich ,  EMELYANOV, Viktor Lvovich ,  SELIVERSTOV, Lev Alexeevich ,  SLONIMSKY, Alexandr Davydovich ,  SKLYAROV, Nikolai Alexeevich ,  TIKHONOV, Vladimir Ivanovich ,  ROGOZHIN, Jury Fedorovich ,  PILIPOSIAN, Pogos Mkrtychevich

IPC: H05K3/46 ,  H05K3/00 ,  H05K1/05 ,  H05K3/42

CPC classification number: H05K3/403 ,  H05K1/056 ,  H05K1/113 ,  H05K1/117 ,  H05K3/0023 ,  H05K3/4076 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/105 ,  H05K2203/1355

Abstract: A multilayer printed circuit board has a metal base (1) with openings (12), the surface of the base and the walls of the openings being covered with an insulation layer (8) obtained by means of applying and mechanical processing, in turn, on both sides, a coating of a powder epoxy composition. An insulation relief (16) of a photo sensitive composition is obtained on the insulation coating, which is then filled with a metal by vacuum deposition. Conductors (4) and contact points (5) of the layer (3) of conducting pattern are obtained by removing the metal from the protruding parts of the relief (16). Then insulation relief (18) is formed corresponding to the location of the contact points (11) and of the commutation bars (10) connecting the layers (3, 6) of the conducting patterns, and is covered with a metal layer. After the removal of the metal from the protruding parts an insulation layer (9) is obtained in which are located the commutation bars (10) and the contact points (11). Then an insulation relief (19) is formed corresponding to the configuration of the layer (6) of the conducting pattern, the metal is applied and mechanically processed so as to obtain conductors (7) with contact points (8) of the layer (6) of the conducting pattern.

公开(公告)号：EP0709886A1

公开(公告)日：1996-05-01

申请号：EP95402404.8

申请日：1995-10-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： Caillat, Patrice

IPC: H01L23/498 ,  H01L23/492

CPC classification number: H01L21/6835 ,  H01L23/4922 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/4038 ,  H05K3/423 ,  H05K2201/09563 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0733 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/2804 ,  Y10T428/2848 ,  H01L2924/00

Abstract: Ce film conducteur anisotrope autoporté comporte une couche (46) de polymère partiellement recuit contenant des trous traversants, des éléments conducteurs en forme de clou (51) remplissant ces trous traversants, comportant une partie centrale et des extrémités, et la partie centrale des clous est constituée d'un matériau dur (52) et chaque extrémité respectivement d'un premier et d'un second matériaux fusibles (44, 54).

Abstract translation: 该装置包括硬化导体固体（52），其具有形成在聚合物材料中的熔融端材料（44,54）的基体，以形成微连接器基体。 形成步骤包括沉积易熔材料层，然后沉积聚合物。 将可熔材料层和聚合物再加热以形成熔融结构。 然后形成额外的层，并进行光刻以形成孔结构。 然后将导体材料添加到孔中，并且将材料加热以形成外孔熔融部分，并剥离下部外层。

公开(公告)号：EP0400332B1

公开(公告)日：1996-01-10

申请号：EP90108033.3

申请日：1990-04-27

Applicant: International Business Machines Corporation

Inventor： DiStefano, Thomas Herman ,  Ehrenberg, Scott Gustave

IPC: H05K3/46 ,  H01L21/48

CPC classification number: H01L21/4857 ,  H05K1/0306 ,  H05K3/0041 ,  H05K3/386 ,  H05K3/4061 ,  H05K3/4076 ,  H05K3/4605 ,  H05K3/4652 ,  H05K2201/0154 ,  H05K2201/09318 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/1581 ,  Y10T29/49165

公开(公告)号：EP0467945B1

公开(公告)日：1995-10-25

申请号：EP90906316.6

申请日：1990-04-11

Applicant: Coates Brothers PLC

Inventor： IVORY, Nicholas Eric ,  COCKETT, Michael Anthony ,  WILSON, Derek Edward

IPC: H05K3/10 ,  H05K3/46

CPC classification number: H05K3/465 ,  H05K3/0023 ,  H05K3/06 ,  H05K3/107 ,  H05K3/108 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2201/09881 ,  H05K2203/054

Abstract: A method of making an insulated patterned layer of an electrically conductive metal includes the steps of: (i) applying a layer of a radiation-curable material (2) to a substrate (1); (ii) imagewise exposing the layer of radiation-curable material to radiation to thereby cure portions (2a) of the layer exposed to such radiation; and (iii) removing the portions (2b) of the layer not exposed to radiation by means of a suitable solvent to thereby produce upon the substrate a patterned layer of cured radiation-curable material; and subsequently introducing electrically conductive metal (4) into the depressions (tracks) in the patterned relief layer.

公开(公告)号：EP0653904A2

公开(公告)日：1995-05-17

申请号：EP94117078.9

申请日：1994-10-28

Applicant: International Business Machines Corporation

Inventor： Arldt, Roy Lynn ,  Boyko, Christina Marie ,  Cayson, Burtran Joe ,  Kozlowski, Richard Michael ,  Kulesza, Joseph Duane ,  Lauffer, John Matthew ,  Liu, Philip Chihchau ,  Markovich, Voya Rista ,  Mahmoud, Issa Said ,  Muska, James Francis ,  Papathomas, Kostas ,  Sabia, Joseph Gene

IPC: H05K3/40 ,  H05K1/09 ,  H01B1/20

CPC classification number: H05K1/113 ,  B32B7/04 ,  H01B1/22 ,  H01B1/24 ,  H01L2224/16235 ,  H05K1/095 ,  H05K1/16 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/4053 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2201/10734 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0207 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0763 ,  Y10S428/901 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24826 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/25

Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes (14) with an epoxy or cyanate fill composition (16). When cured and overplated, the fill composition (16) provides support for the solder joint (22) and provides a flat solderable surface (18) for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Abstract translation: 本发明允许焊点直接作出的通孔和通孔，而不焊料为芯吸到通孔或通孔，通过与环氧树脂或氰酸孔中填充电镀来填充组合物。 当固化时，用镀覆，所述填充物组合物提供了对焊点并提供用于连接间的平坦焊接表面。 在某些实施方案中，固化的填充物组合物，提供的是导电的进一步的优点。 因此，本发明涉及若干新颖方法，用于通过与寻求填充物组合物填充通孔，和设在通孔和通孔的电阻。

公开(公告)号：EP0645952A1

公开(公告)日：1995-03-29

申请号：EP94114083.2

申请日：1994-09-08

Applicant: ROGERS CORPORATION

Inventor： Daigle, Robert C. ,  Smith, David W. ,  Olenick, John A. ,  Arthur, David J. ,  Swei, Gwo S.

IPC: H05K3/46 ,  H01L21/48

CPC classification number: H01L21/4857 ,  H01L23/49894 ,  H01L23/5383 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0289 ,  H05K3/20 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K3/328 ,  H05K3/423 ,  H05K3/4617 ,  H05K3/4632 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4658 ,  H05K3/4682 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/09563 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In accordance with the present invention, a circuit assembly is manufactured in an additive process using at least one layer of a fluoropolymer composite material and a conductive material. The conductive layers are plated, and the fluoropolymer composite layers are laminated. The use of the filled fluoropolymeric composite eliminates the need for a barrier metal layer between the insulation and the conductors. A plurality of these circuit assemblies are stacked, one on top of the other. At least, selected exposed locations of the conductive material comprise a diffusible conductive material (e.g., gold). Once stacked the circuit assemblies are subjected to lamination under heat and pressure to simultaneously fuse adjacent fluoropolymer composite material and diffuse adjacent diffusible conductive material together to form an integral multilayer circuit having solid conductive interconnects.

Abstract translation: 根据本发明，使用至少一层含氟聚合物复合材料和导电材料的添加方法制造电路组件。 对导电层进行电镀，层压含氟聚合物复合层。 使用填充的氟聚合物复合材料不需要隔离层和导体之间的阻挡金属层。 多个这些电路组件一个在另一个之上堆叠。 至少，导电材料的选定的暴露位置包括可扩散的导电材料（例如，金）。 一旦堆叠，电路组件在热和压力下进行层压，以同时熔化相邻的含氟聚合物复合材料并将相邻的可扩散导电材料扩散在一起以形成具有固体导电互连的整体多层电路。

公开(公告)号：EP0557278B1

公开(公告)日：1994-12-07

申请号：EP91904608.6

申请日：1991-02-01

Applicant: International Business Machines Corporation

Inventor： CHANG, Kenneth ,  CZORNYJ, George ,  FAROOQ, Mukta, Shaji ,  KUMAR, Ananda, Hosakere ,  PITTLER, Marvin, S. ,  STEIMEL, Heinz, Otto

IPC: H01L21/48 ,  H01L23/538

CPC classification number: H01L21/76808 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/76807 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/184 ,  H05K3/388 ,  H05K3/465 ,  H05K3/4661 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/107

Abstract: A method of making a multilayer thin film structure on the surface of a dielectric substrate which includes the steps of: a) forming a multilayer thin film structure including the steps of: applying a first layer of dielectric polymeric material on the surface of a dielectric substrate, applying a second layer of dielectric polymeric material over the first layer of polymeric material wherein the second polymeric material is photosensitive, imagewise exposing and developing the second polymeric material to form a feature therein, the second layer feature in communication with at least one feature formed in the first polymeric material; and b) filling the features in the entire multilayer structure simultaneously with conductive material. Preferably, the first layer feature is a via and the second layer feature is a capture pad or wiring channel. Also disclosed is a multilayer thin film structure made by this method.

公开(公告)号：EP0582881A1

公开(公告)日：1994-02-16

申请号：EP93111860.8

申请日：1993-07-23

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kubota, Kenjin, c/o Murata Manufacturing Co., Ltd. ,  Sakai, Norio, c/o Murata Manufacturing Co., Ltd. ,  Kawabata, Shoichi, c/o Murata Manufact. Co., Ltd.

IPC: H01G1/147 ,  H05K3/40 ,  H01G1/035 ,  H01L21/66

CPC classification number: H01G4/232 ,  H01G2/065 ,  H01L22/20 ,  H01L22/32 ,  H01L23/10 ,  H01L23/49805 ,  H01L2924/014 ,  H01L2924/16152 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/403 ,  H05K3/4061 ,  H05K2201/09181 ,  H05K2201/09563 ,  H05K2201/09845 ,  Y10T29/435 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: In order to provide a multilayer electronic component (10) which can reduce arrangement pitches for external electrodes (12), via holes (19) filled up with conductive materials (18) are provided in a mother laminate (14), which is obtained by stacking a plurality of insulating sheets (16, 17) with interposition of conductor films (23, 24), in positions parted by cutting. The conductive materials (18) define external electrodes (12) of individual multilayer electronic components (10) which are obtained by cutting the mother laminate (14). No specific step is required for forming the external electrodes (12), and characteristics of each multilayer electronic component (10) can be efficiently measured in the state of the mother laminate (14).

Abstract translation: 为了通过孔提供一种多层电子元件（10），其可以降低排列间距为外部电极（12）（19）填充有导电材料（18）在母层叠体（14）被提供，其全部通过以下方式获得 堆叠绝缘片（16，17）的多个与通过切割分开的位置的导体膜（23，24）的插入。 导电材料（18）限定了通过切割母层叠体（14）所得到的各层叠型电子部件（10）的外部电极（12）。 没有具体的步骤是必需的用于形成外部电极（12），并且每个多层电子元件（10）的特征可在母层叠体（14）的状态下被有效地测定。

公开(公告)号：EP0549791A1

公开(公告)日：1993-07-07

申请号：EP91909937.4

申请日：1991-04-01

Applicant: FILIAL VSESOJUZNOGO NAUCHNO-ISSLEDOVATELSKOGO INSTITUTA ELEKTROMEKHANIKI

Inventor： ADASKO, Vladimir Iosifovich ,  VARDENBURG, Arnold Kurtovich ,  EMELYANOV, Alexandr Lvovich ,  EMELYANOV, Viktor Lvovich ,  SELIVERSTOV, Lev Alexeevich ,  SLONIMSKY, Alexandr Davydovich ,  SKLYAROV, Nikolai Alexeevich ,  TIKHONOV, Vladimir Ivanovich ,  ROGOZHIN, Jury Fedorovich ,  PILIPOSIAN, Pogos Mkrtychevich

IPC: H05K3/46 ,  H05K3/00 ,  H05K1/05 ,  H05K3/42

CPC classification number: H05K3/403 ,  H05K1/056 ,  H05K1/113 ,  H05K1/117 ,  H05K3/0023 ,  H05K3/4076 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/105 ,  H05K2203/1355

Abstract: Die Mehrlagenleiterplatte besitzt ein metallisches Substrat (1) mit Löchern (12), wobei die Oberfläche des Substrats (1) und die Wände der Löcher (12) mit einer Isolationsschicht (9) bedeckt sind, die durch Auftragung und mechanische Bearbeitung der Reihe nach auf zwei Seiten eines Überzuges aus einer pulverförmigen Epoxidharzkomposition hergestellt wird. Auf dem Isolierstoffüberzug (2) ehrält man ein Isolationsrelief (16) aus einer fotoempfindlichen Komposition, welches Relief mit Metall durch Abscheibung im Vakuum ausgefüllt wird. Durch Entfernung des Metalls von den hervorstehenden Teilen des Reliefs (16) erhält man Leiter (4) und Kontaktflächen (5) einer Leiterbildschicht (5). Dann formiert man ein Isolationsrelief (18), das der Anordnung von Kontaktflächen (11) und Schalthöckern (10) entspricht, welche die Leiterbildschichten (3,6) verbinden, und bedeckt es mit einer Metallschicht. Nach der Entfernung des Metalls von den hervorstehenden Teilen erhält man eine Isolationsschicht (9), in der sich die Schalthöcker (10) und die Kontaktflächen (11) befinden. Des weiteren formiert man ein Isolationsrelief (19), das der Konfiguration einer Leiterbildschicht (6) entspricht, bringt das Metall auf und bearbeitet es mechanisch, indem man die Leiter (7) mit Kontaktflächen (8) der Leiterbildschicht (6) erhält.

Abstract translation: 多层印刷电路板具有带有孔（12）的金属基板（1），基板（1）的表面和孔（12）的壁被绝缘层（9）覆盖，绝缘层（9）由连续的 在粉末环氧树脂组合物的涂层的两面上进行涂布和机械处理。 绝缘材料涂层（2）产生由感光组合物组成的绝缘浮雕（16），该浮雕通过真空沉积被金属填充。 从浮雕（16）的突出部分去除金属产生导电图案层（5）的导体（4）和接触表面（5）。 然后形成对应于连接导体图案层（3,6）的接触表面（11）和连接凸块（10）的布置的绝缘释放件（18），并且浮雕被金属层覆盖。 在从突出部分移除金属之后，获得连接凸起（10）和接触表面（11）所在的绝缘层（9）。 另外，形成与导体图案层（6）的构造相对应的绝缘解除装置（19），金属被施加并机械加工，以便制造具有接触表面（8）的导体（7） 导体图案层（6）。

公开(公告)号：EP0540451A2

公开(公告)日：1993-05-05

申请号：EP92480153.3

申请日：1992-10-09

Applicant: International Business Machines Corporation

Inventor： Sachdev, Krishna Gandhi ,  McGuire, Kathleen Mary ,  Kellner, Benedikt Maria Johannes ,  Sorce, Peter Jerome

IPC: H01L21/48 ,  H05K3/46

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L23/5383 ,  H01L2924/0002 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/007 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/423 ,  H05K3/445 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4641 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0152 ,  Y10T29/49165 ,  Y10T428/12361 ,  Y10T428/12382 ,  Y10T428/12556 ,  Y10T428/12569 ,  Y10T428/12806 ,  Y10T428/12812 ,  Y10T428/24777 ,  Y10T428/31678 ,  Y10T428/31681 ,  H01L2924/00

Abstract: This invention relates generally to a structure and process for thin film interconnect, and more particularly to a structure and process for a multilayer thin film interconnect structure (75) with improved dimensional stability and electrical performance. The invention further relates to a process of fabrication of the multilayer thin film structures (75). The individual thin film structure (50) is termed a compensator, and functions as both a ground/reference plane and as a stabilizing entity with regard to dimensional integrity. The compensator (50) is comprised primarily of a metal sheet (17) having a metallized via pattern (41) and high-temperature stable polymer (25) as an insulator.

Abstract translation: 本发明一般涉及薄膜互连的结构和工艺，更具体地说涉及具有改进的尺寸稳定性和电性能的多层薄膜互连结构的结构和工艺。 本发明还涉及多层薄膜结构的制造方法。 单个薄膜结构被称为补偿器，并且在尺寸完整性方面起到地面/参考平面和稳定实体的作用。 补偿器主要包括具有金属化通孔图案和作为绝缘体的高温稳定聚合物的金属片。