公开(公告)号：EP2800130A1

公开(公告)日：2014-11-05

申请号：EP13165820.5

申请日：2013-04-29

申请人： ABB Technology AG

发明人： Brem, Franziska ,  Liu, Chunlei ,  Duran, Hamit

IPC分类号： H01L21/60 ,  H01L23/13 ,  H01L23/495 ,  H01L23/051

CPC分类号： H01L24/92 ,  H01L21/6836 ,  H01L23/051 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/04026 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/26135 ,  H01L2224/26165 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/32258 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/33181 ,  H01L2224/83007 ,  H01L2224/83101 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/8321 ,  H01L2224/83222 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A method for bonding an electronics chip (10) to a substrate (12), the method comprising the steps of: coating a bonding area (14) of the chip (10) with a first metal layer (18); providing a bonding area (24) of the substrate (12) and/or the bonding area (14) of the chip (10) with a low melting point metal layer (30), wherein the bonding area (24) of the substrate (12) comprises a second metal layer (28); attaching a spacer (20) to the chip (10) and/or the substrate (12); positioning and fixing the chip (10) on the substrate (12); and transient liquid phase bonding the chip (10) to the substrate (12) by melting the low melting point layer (30), wherein the spacer (20) provides a specific distance between the first metal layer (18) and the second metal layer (28).

摘要翻译： 一种用于电子芯片（10）的键合到基底（12）的方法，该方法包括以下步骤：涂覆所述芯片（10）与第一金属层（18）的接合区域（14）; 提供所述基板的基板的接合区（24）（12）和/或芯片（10）具有低的低熔点金属层（30）的接合区域（14），其中，所述结合区域（24）（ 12）包括第二金属层（28）; 附接的间隔件（20）与芯片（10）和/或基底（12）; 定位和固定在基板上的芯片（10）（12）; 和瞬态液相接合芯片（10）到所述衬底（12）通过熔化低熔点层（30），其中所述间隔物（20）提供所述第一金属层（18）和第二金属层之间的特定距离 （28）。

公开(公告)号：EP0628997A3

公开(公告)日：1995-09-06

申请号：EP94304221.8

申请日：1994-06-10

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Umehara, Norito, Japan Texas Instruments Co. Ltd.

IPC分类号： H01L23/495

CPC分类号： H01L24/85 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/27013 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83141 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20752 ,  Y10T29/49121 ,  Y10T29/49146 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599

摘要： Semiconductor device package 53 having a lead frame with a mounting pad 31 smaller than the IC chip 10 mounted thereon, and a method of making a semiconductor device package based on wire bonding using a heater insert 38 with a mounting pad insertion concave part 51. Separation between the mounting pad and an encapsulating resin is eliminated, cracks are not created in the resin, or are considerably reduced, and warpage of the package can be prevented. Also, bonding of wires between leads and respective bonding pads 17 on the chip 10 can be executed stably and efficiently.

公开(公告)号：EP2915190A2

公开(公告)日：2015-09-09

申请号：EP13850327.1

申请日：2013-10-23

申请人： Raytheon Company

发明人： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC分类号： B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

公开(公告)号：EP2260508A1

公开(公告)日：2010-12-15

申请号：EP09731239.1

申请日：2009-04-07

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： DI CIOCCIO, Léa ,  GROSSI, François ,  GUEGUEN, Pierric ,  VANDROUX, Laurent

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L21/98

CPC分类号： H01L24/83 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/90 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/80004 ,  H01L2224/80143 ,  H01L2224/81136 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83002 ,  H01L2224/83141 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/95085 ,  H01L2224/95146 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/0665 ,  H01L2924/00

摘要： The invention relates to a method of forming, on the surface of a substrate (2), at least one hydrophilic attachment zone (12) for the purpose of self-assembling a component or a chip (3), in which a hydrophobic zone (20), which delimits said hydrophilic attachment zone, is produced.

公开(公告)号：EP0951736A1

公开(公告)日：1999-10-27

申请号：EP97951405.0

申请日：1997-12-19

申请人： TELEFONAKTIEBOLAGET L M ERICSSON (publ)

发明人： HESSELBOM, Lillebror, Hjalmar ,  BODÖ, Jan, Peter

IPC分类号： H01L21 ,  H01L29

CPC分类号： H01L24/83 ,  H01L24/26 ,  H01L29/0657 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/83141 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： This invention belongs to a mounting technology for aligning parts, a self-aligned elastic positioning. A problem this invention solves is alignement of parts without using mechanical fine pre-alignment. Wherein one part has elastic bumps, another part has V-grooves and the parts fit into each other. The invention is using elastic material for the bumps to fit the V-grooves. Whereas the bumps are made of elastic material and shaped partly to the V-bumps by moulding. The two parts can slide along in the direction perpendicular to the plane of the surface of the part. The movement in the perpendicular direction can be controled by an external force. This means that the bumps and V-grooves have good alignment in xy-orientation and are also partially aligned in z-orientation. The elasticity of the bumps allows for thermal expansion differences without stresses to the parts while maintaining high precision alignment at a point. By using this type of parts they can be disassembled and be replaced without destroying the alignment features.

公开(公告)号：EP0312217A1

公开(公告)日：1989-04-19

申请号：EP88308865.0

申请日：1988-09-23

申请人： AT&T Corp.

发明人： Pfeiffer, Loren Neil ,  Wong, Yiu-Huen

IPC分类号： H01L21/60 ,  H01L23/14 ,  H01L29/06

CPC分类号： H01L24/81 ,  H01L23/13 ,  H01L23/147 ,  H01L29/0657 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83141 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/00

摘要： Integrated circuit chips (11) are attached, and electrically connected across a desired distance, to a substrate (31) in a facing relationship; electrical interconnection typically involves solder connections (52) between facing contact pads. Positive control of the desired distance is achieved by chip and/or substrate surface spacer features such as, e.g., miniature pyramids (33) - optionally in combination with matching opposite features. Conveniently, in the case of silicon chips on a silicon substrate, as well as in the case of analogous Group III-V compound semiconductor structures, surface spacer features are produced by orientation dependent chemical etching.

摘要翻译： 集成电路芯片（11）以面对的关系附接并跨越期望的距离电连接到基板（31）; 电互连通常包括在相对的接触焊盘之间的焊接连接（52）。 通过芯片和/或衬底表面间隔物特征（例如微型金字塔（33））可选地与匹配的相对特征组合来实现期望距离的正向控制。 方便地，在硅衬底上的硅芯片的情况下，以及类似的III-V族化合物半导体结构的情况下，通过取向依赖的化学蚀刻产生表面间隔物特征。

公开(公告)号：EP2915190A4

公开(公告)日：2016-09-14

申请号：EP13850327

申请日：2013-10-23

申请人： RAYTHEON CO

发明人： GOOCH ROLAND ,  DIEP BUU ,  KOCIAN THOMAS ALLAN ,  BLACK STEPHEN H ,  KENNEDY ADAM M

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC分类号： B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

摘要翻译： 形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的第一组和第二组的组合厚度在结合所述器件晶片和所述盖晶片时限定了整合的键合间隙控制结构。

公开(公告)号：EP2919261A1

公开(公告)日：2015-09-16

申请号：EP15158423.2

申请日：2015-03-10

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  RENAULT S.A.S.

发明人： Chambion, Bertrand ,  Bedoin, Alexis

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： B81C1/00341 ,  B81C2203/032 ,  C08G59/18 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/27416 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81903 ,  H01L2224/83141 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2924/12041 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

摘要： Le procédé d'hybridation d'un premier élément microélectronique (100) avec un deuxième élément microélectronique (200) comporte une étape de rapprochement des premier et deuxième éléments microélectroniques (100, 200) de telle sorte à générer un collage par interaction de premier et deuxième composants (104, 202) d'une colle bi-composants. Au moins un premier organe (103) s'étend dudit premier élément microélectronique (100), le premier composant (104) de la colle bi-composants étant associé audit premier élément microélectronique (100), et au moins un deuxième organe (201) s'étend dudit deuxième élément microélectronique (200), le deuxième composant (202) de la colle bi-composants étant associé audit deuxième élément microélectronique (200). Le procédé comporte une étape de mélange des premier et deuxième composants (104, 202) mise en oeuvre par lesdits au moins un premier et deuxième organes (103, 201) lors de l'étape de rapprochement, et en ce qu'au terme de l'étape de rapprochement la distance (d1) séparant le premier élément microélectronique (100) du deuxième élément microélectronique (200) est inférieure à la hauteur cumulée dudit au moins un premier organe (103) et dudit au moins un deuxième organe (201) avant rapprochement.

公开(公告)号：EP2250670B1

公开(公告)日：2011-08-24

申请号：EP09726241.4

申请日：2009-02-19

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： SAINT-PATRICE, Damien ,  MARION, François

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/3511 ,  Y10T29/49139 ,  H01L2924/00012

摘要： The invention relates to a method for electrically connecting a component comprising, on one face, a set of conductive inserts, to another component comprising conductive buried regions, said inserts resting on conductive blocks advantageously produced from a deformable material and positioned at the surface of the component. The surface of the block, which is to come into contact with the insert, has at least one dimension larger than that of the buried region and a higher ductility than that of the material forming the insert and that of the material forming the buried region.

公开(公告)号：EP0628997B1

公开(公告)日：2002-04-10

申请号：EP94304221.8

申请日：1994-06-10

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Umehara, Norito, Japan Texas Instruments Co. Ltd.

IPC分类号： H01L23/495

CPC分类号： H01L24/85 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/27013 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83141 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20752 ,  Y10T29/49121 ,  Y10T29/49146 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599