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    Linear Cluster Deposition System
    4.
    发明申请
    Linear Cluster Deposition System 审中-公开
    线性簇沉积系统

    公开(公告)号：US20120058630A1

    公开(公告)日：2012-03-08

    申请号：US12877775

    申请日：2010-09-08

    申请人： William E. Quinn ,  Alexander Gurary ,  Ajit Paranjpe ,  Maria D. Ferreira ,  Roger P. Fremgen, JR. ,  Eric A. Armour

    发明人： William E. Quinn ,  Alexander Gurary ,  Ajit Paranjpe ,  Maria D. Ferreira ,  Roger P. Fremgen, JR. ,  Eric A. Armour

    IPC分类号： H01L21/36 ,  C23C16/06 ,  C23C16/08 ,  C23C16/00 ,  C23C16/44

    摘要： A linear cluster deposition system includes a plurality of reaction chambers positioned in a linear horizontal arrangement. First and second reactant gas manifolds are coupled to respective process gas input port of each of the reaction chambers. An exhaust gas manifold having a plurality of exhaust gas inputs is coupled to the exhaust gas output port of each of the plurality of reaction chambers. A substrate transport vehicle transports at least one of a substrate and a substrate carrier that supports at least one substrate into and out of substrate transfer ports of each of the reaction chambers. At least one of a flow rate of process gas into the process gas input port of each of the reaction chambers and a pressure in each of the reaction chambers being chosen so that process conditions are substantially the same in at least two of the reaction chambers.

    摘要翻译： 线性簇沉积系统包括以线性水平布置定位的多个反应室。 第一和第二反应气体歧管连接到每个反应室的相应工艺气体输入口。 具有多个排气输入的废气歧管与多个反应室中的每一个的废气输出端口连接。 基板输送车辆将基板和基板载体中的至少一个输送到每个反应室的基板输送口中并至少支撑至少一个基板。 选择每个反应室的工艺气体进入工艺气体输入口的流量和每个反应室中的压力中的至少一个，使得工艺条件在至少两个反应室中基本相同。

    Multi-Chamber CVD Processing System
    5.
    发明申请
    Multi-Chamber CVD Processing System 审中-公开
    多室CVD处理系统

    公开(公告)号：US20110290175A1

    公开(公告)日：2011-12-01

    申请号：US13185450

    申请日：2011-07-18

    申请人： Ajit Paranjpe ,  Eric A. Armour ,  William E. Quinn

    发明人： Ajit Paranjpe ,  Eric A. Armour ,  William E. Quinn

    IPC分类号： C30B25/02 ,  C30B25/08 ,  C30B25/12

    CPC分类号： C23C16/4582 ,  C23C16/54 ,  C30B25/025 ,  C30B35/00

    摘要： A multi-chamber CVD system includes a plurality of substrate carriers where each substrate carrier is adapted to support at least one substrate. A plurality of enclosures are each configured to form a deposition chamber enclosing one of the plurality of substrate carriers to maintain an independent chemical vapor deposition process chemistry for performing a processing step. A transport mechanism transports each of the plurality of substrate carriers to each of the plurality of enclosures in discrete steps that allow processing steps to be performed in the plurality of enclosures for a predetermined time. In some embodiments, the substrate carrier can be rotatable.

    摘要翻译： 多室CVD系统包括多个衬底载体，其中每个衬底载体适于支撑至少一个衬底。 多个外壳各自被配置为形成包围多个基板载体之一的沉积室，以维持用于执行处理步骤的独立化学气相沉积工艺化学品。 传送机构以离散步骤将多个基板载体中的每一个传送到多个外壳中的每一个，从而允许在多个外壳中执行预定时间的处理步骤。 在一些实施例中，衬底载体可以是可旋转的。

    PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES
    8.
    发明申请
    PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES 有权
    DEEP TRENCHES DOPED SILICON FILL的工艺顺序

    公开(公告)号：US20080318441A1

    公开(公告)日：2008-12-25

    申请号：US12199402

    申请日：2008-08-27

    申请人： Ajit Paranjpe ,  Somnath Nag

    发明人： Ajit Paranjpe ,  Somnath Nag

    IPC分类号： H01L21/762

    CPC分类号： C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

    摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

    摘要翻译： 提供了一种用于无缝填充深沟槽结构的原位掺杂非晶硅的方法，其中第一填充以使得膜沉积从沟槽底部向上发生的方式进行，其中步骤覆盖良好地超过 100％。 在第二填充步骤中，改变沉积条件以减少掺杂剂对沉积速率的影响，并且沉积以超过第一填充的沉积速率的速率进行。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

    Process sequence for doped silicon fill of deep trenches
    9.
    发明授权
    Process sequence for doped silicon fill of deep trenches 有权
    深沟槽掺杂硅填充工艺顺序

    公开(公告)号：US07446366B2

    公开(公告)日：2008-11-04

    申请号：US11420893

    申请日：2006-05-30

    申请人： Ajit Paranjpe ,  Somnath Nag

    发明人： Ajit Paranjpe ,  Somnath Nag

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

    摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

    摘要翻译： 提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积 向上。 通过这个第一次填充，达到100％以上的步骤覆盖率。 在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

    POLY-SILICON-GERMANIUM GATE STACK AND METHOD FOR FORMING THE SAME
    10.
    发明申请
    POLY-SILICON-GERMANIUM GATE STACK AND METHOD FOR FORMING THE SAME 失效
    聚硅锗门盖及其形成方法

    公开(公告)号：US20060231925A1

    公开(公告)日：2006-10-19

    申请号：US11420940

    申请日：2006-05-30

    申请人： Ajit Paranjpe ,  Kangzhan Zhang

    发明人： Ajit Paranjpe ,  Kangzhan Zhang

    IPC分类号： H01L27/082

    CPC分类号： H01L21/28044 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28282 ,  H01L21/823828 ,  H01L29/4925 ,  H01L29/513

    摘要： A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin α-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second α-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

    摘要翻译： 已经描述了与常规CMOS栅极堆叠相比增加反转电容的CMOS栅极堆叠。 使用多晶硅栅极，代替栅极电介质层附近的常规多晶硅栅极，增加了可被激活的注入掺杂剂的量。 这种增加克服了限制常规CMOS栅极堆叠中的反相电容的多晶硅耗尽问题。 为了将多晶硅层整合到栅极堆叠中，在栅极介电层和多晶硅层之间沉积薄的α-Si层。 为了确保适当的自对准硅化物形成，多晶硅层被覆盖在多晶硅层上。 为了获得多晶SiGe上的细晶粒多晶硅，在多晶硅层和多晶硅层之间沉积第二个α-Si层。