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1.发明申请公开(公告)号：US20190006333A1
公开(公告)日：2019-01-03
申请号：US16017719
申请日：2018-06-25
摘要： A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.
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公开(公告)号：US20160148866A1
公开(公告)日：2016-05-26
申请号：US14555124
申请日：2014-11-26
申请人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
发明人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
IPC分类号： H01L23/528 , H01L21/768 , H01L21/288 , H01L23/00
CPC分类号： H01L21/2885 , H01L21/76802 , H01L21/76879 , H01L23/48 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L24/13 , H01L2224/1302 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.
摘要翻译： 一些示例形式涉及电子封装的电互连。 电互连包括介电层，其包括形成在电介质层的一个表面中的沟槽和填充沟槽并在电介质层的一个表面上方延伸的信号导体。 电互连还包括安装在电介质层的相对侧上的导电参考层。 当电流通过信号导体时，导电参考层与信号导体电磁耦合。
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3.发明申请METHOD TO ENABLE CONTROLLED SIDE CHIP INTERCONNECTION FOR 3D INTEGRATED PACKAGING SYSTEM 有权用于3D集成包装系统的控制侧切片互连的方法公开(公告)号：US20130341803A1
公开(公告)日：2013-12-26
申请号：US13997041
申请日：2012-06-25
IPC分类号： H01L25/065
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译： 描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。 在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。 还包括具有半导体管芯的第二基本水平布置的第二MSD结构。 中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。
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公开(公告)号：US20200170113A1
公开(公告)日：2020-05-28
申请号：US16662918
申请日：2019-10-24
申请人： Chaitanya Sreerama , Bok Eng Cheah , Jackson Chung Peng Kong , Yew San Lim , Stephen Harvey Hall , Eric C. Gantner
发明人： Chaitanya Sreerama , Bok Eng Cheah , Jackson Chung Peng Kong , Yew San Lim , Stephen Harvey Hall , Eric C. Gantner
摘要： A flexible electronic interconnect comprises a first dielectric layer including a first surface and second surface opposite the first surface; a plurality of conductors disposed on the first surface of the first dielectric layer and arranged spaced apart from each other using a conductor spacing; and a first plurality of conductive shields disposed on the second surface of the first dielectric layer and arranged spaced apart from each other using a conductive shield spacing. The first plurality of conductive shields is arranged opposite the plurality of conductors and the conductive shield spacing is arranged opposite the conductor spacing.
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公开(公告)号：US20200091040A1
公开(公告)日：2020-03-19
申请号：US16451521
申请日：2019-06-25
IPC分类号： H01L23/48 , H01L23/528
摘要： Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.
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公开(公告)号：US20190295966A1
公开(公告)日：2019-09-26
申请号：US16469073
申请日：2017-11-27
IPC分类号： H01L23/64 , H01L23/00 , H01L23/498 , H01L21/48
摘要： A device and method of utilizing conductive thread interconnect cores. Substrates using conductive thread interconnect cores are shown. Methods of creating a conductive thread interconnect core are shown.
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公开(公告)号：US20190148269A1
公开(公告)日：2019-05-16
申请号：US16018635
申请日：2018-06-26
IPC分类号： H01L23/498 , H01L23/00 , H01L21/768
摘要： A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
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公开(公告)号：US20190006277A1
公开(公告)日：2019-01-03
申请号：US16017652
申请日：2018-06-25
IPC分类号： H01L23/522 , H01L49/02 , H01L25/16 , H01L25/065 , H01L23/00 , H01G4/30
摘要： A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
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公开(公告)号：US20170185102A1
公开(公告)日：2017-06-29
申请号：US14998067
申请日：2015-12-24
IPC分类号： G06F1/16 , H01R13/10 , H01R13/426 , H01R12/70
CPC分类号： G06F1/163 , A41D1/005 , G06F1/1656 , H01R4/58 , H01R12/7011 , H01R12/718 , H05K1/11 , H05K3/4007 , H05K2201/09027
摘要： Various embodiments are generally directed to an apparatus, method and other techniques to provide a interface component including a housing comprising a first shell portion and a second shell portion, the first shell portion forming an extended portion for the housing and comprising a retention track engageable a counterpart retention track. The interface component to include a printed circuit board disposed within the housing, the printed circuit board comprising a plurality of contact pins each comprising a contact hole and a retention bump and a socket to couple with a stud.
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10.发明授权Method to enable controlled side chip interconnection for 3D integrated packaging system 有权实现3D集成封装系统的可控侧芯片互连的方法公开(公告)号：US09136251B2
公开(公告)日：2015-09-15
申请号：US13997041
申请日：2012-06-25
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译： 描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。 在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。 还包括具有半导体管芯的第二基本水平布置的第二MSD结构。 中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。
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