-
1.发明申请公开(公告)号：US20190006333A1
公开(公告)日：2019-01-03
申请号：US16017719
申请日：2018-06-25
摘要： A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.
-
2.发明申请公开(公告)号：US20200006246A1
公开(公告)日：2020-01-02
申请号：US16402522
申请日：2019-05-03
IPC分类号： H01L23/552 , H01L23/16 , H01L23/538 , H01L23/00 , H01L25/10 , H01L21/48 , H01L25/00
摘要： A stiffener includes an integrated cable-header recess that couples a semiconductor package substrate flexible cable. The flexible cable connects to a device on a board without using interconnections that are arrayed through the board. A semiconductive die is coupled to the semiconductor package substrate and flexible cable through the cable-header recess.
-
3.发明申请公开(公告)号：US20190181097A1
公开(公告)日：2019-06-13
申请号：US16018984
申请日：2018-06-26
摘要： A stiffener includes a through-stiffener interconnect that couples a semiconductor package substrate to a package-on-package device. The through-stiffener interconnect is insulated by a through-stiffener dielectric within a through-stiffener contact corridor. A semiconductive die is coupled to the semiconductor package substrate and to the package-on-package device.
-
公开(公告)号：US20210183779A1
公开(公告)日：2021-06-17
申请号：US17024182
申请日：2020-09-17
IPC分类号： H01L23/538 , H01L23/00 , H01L21/50
摘要： Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.
-
公开(公告)号：US20210066185A1
公开(公告)日：2021-03-04
申请号：US16912619
申请日：2020-06-25
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528
摘要： Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.
-
公开(公告)号：US20190206698A1
公开(公告)日：2019-07-04
申请号：US16325665
申请日：2016-09-27
IPC分类号： H01L21/48 , H01L23/48 , H01L23/538 , H01L23/552 , H01L25/065 , H01L25/00 , H01L29/06
CPC分类号： H01L21/48 , H01L23/00 , H01L23/48 , H01L23/538 , H01L23/552 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1432 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/3025
摘要： A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
-
公开(公告)号：US20180088627A1
公开(公告)日：2018-03-29
申请号：US15280994
申请日：2016-09-29
IPC分类号： G06F1/16 , H05K1/03 , H05K1/02 , H05K1/18 , H01L23/538 , H01L25/065 , H01L25/00 , H05K3/30 , H05K3/46 , H01L23/00 , H05K3/28 , H01L23/66
CPC分类号： G06F1/163 , H01L23/5385 , H01L23/5387 , H01L23/564 , H01L23/66 , H01L25/0655 , H01L25/50 , H01L2223/6627 , H05K1/038 , H05K1/189 , H05K2201/10098
摘要： Various embodiments disclosed relate to a wearable electronic device. One embodiment includes of a wearable electronic device includes a first flexible layer. The first flexible layer includes a first surface and a second surface that is substantially parallel to the first surface. A first electrical component and a second electrical component is attached to the second surface. A transmission line connects the first electrical component and the second electrical component. A voltage reference trace connected to a voltage reference source attached to at least one of the first electrical component or the second electrical component. The device further includes a second flexible layer. The second flexible layer includes a third surface that is substantially parallel to the second surface and facing the second surface. The second flexible layer also includes a fourth surface. The device further includes a voltage reference plane attached to the third surface. An interconnection is formed between the voltage reference trace and the voltage reference plane.
-
公开(公告)号：US20200091093A1
公开(公告)日：2020-03-19
申请号：US16450266
申请日：2019-06-24
摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.
-
公开(公告)号：US20160148866A1
公开(公告)日：2016-05-26
申请号：US14555124
申请日：2014-11-26
申请人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
发明人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
IPC分类号： H01L23/528 , H01L21/768 , H01L21/288 , H01L23/00
CPC分类号： H01L21/2885 , H01L21/76802 , H01L21/76879 , H01L23/48 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L24/13 , H01L2224/1302 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.
摘要翻译： 一些示例形式涉及电子封装的电互连。 电互连包括介电层，其包括形成在电介质层的一个表面中的沟槽和填充沟槽并在电介质层的一个表面上方延伸的信号导体。 电互连还包括安装在电介质层的相对侧上的导电参考层。 当电流通过信号导体时，导电参考层与信号导体电磁耦合。
-
10.发明申请METHOD TO ENABLE CONTROLLED SIDE CHIP INTERCONNECTION FOR 3D INTEGRATED PACKAGING SYSTEM 有权用于3D集成包装系统的控制侧切片互连的方法公开(公告)号：US20130341803A1
公开(公告)日：2013-12-26
申请号：US13997041
申请日：2012-06-25
IPC分类号： H01L25/065
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译： 描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。 在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。 还包括具有半导体管芯的第二基本水平布置的第二MSD结构。 中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。
-
-
-
-
-
-
-
-
-
搜索结果
44 条记录 (耗时 0.037 秒)
