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    Interconnect structure for integrated circuits having improved electromigration characteristics
    3.
    发明授权
    Interconnect structure for integrated circuits having improved electromigration characteristics 有权
    具有改进的电迁移特性的集成电路的互连结构

    公开(公告)号：US08056039B2

    公开(公告)日：2011-11-08

    申请号：US12128973

    申请日：2008-05-29

    申请人： Kaushik Chanda ,  Ronald Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

    发明人： Kaushik Chanda ,  Ronald Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

    IPC分类号： G06F17/50

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

    摘要翻译： 用于集成电路（IC）装置的互连结构包括细长的导电线，其包括形成在第一宽度w 1处的一个或多个段以及以一个或多个附加宽度w2形成的一个或多个段。 。 。 wN，其中第一宽度比一个或多个附加宽度中的每一个窄; 其中形成在第一宽度处的一个或多个导电段的总长度L1与总长度L2的关系。 。 。 选择以一个或多个附加宽度形成的一个或多个导电段的LN，使得对于给定的导电线承载的电流，相对于电迁移短长度效应益处的临界长度被保​​持为 导线的总长度L = L1 + L2 +。 。 。 + LN，无论临界长度如何，满足最小设计长度。

    Air gap in integrated circuit inductor fabrication
    7.
    发明授权
    Air gap in integrated circuit inductor fabrication 有权
    集成电路电感器制造中的气隙

    公开(公告)号：US07566627B2

    公开(公告)日：2009-07-28

    申请号：US11771298

    申请日：2007-06-29

    申请人： Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    发明人： Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    IPC分类号： H01L21/20

    CPC分类号： H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

    摘要翻译： 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。

    Use of supercritical fluid for low effective dielectric constant metallization
    9.
    发明授权
    Use of supercritical fluid for low effective dielectric constant metallization 有权
    超临界流体用于低有效介电常数金属化

    公开(公告)号：US07179747B2

    公开(公告)日：2007-02-20

    申请号：US10902243

    申请日：2004-07-28

    申请人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

    发明人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

    IPC分类号： H01L21/311 ,  H01L21/302

    CPC分类号： H01L23/5329 ,  H01L21/31116 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

    摘要翻译： 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。

    Stacked interconnect structure between copper lines of a semiconductor circuit
    10.
    发明申请
    Stacked interconnect structure between copper lines of a semiconductor circuit 审中-公开
    半导体电路铜线之间的堆叠互连结构

    公开(公告)号：US20050082089A1

    公开(公告)日：2005-04-21

    申请号：US10688452

    申请日：2003-10-18

    申请人： Stephan Grunow ,  Satyavolu Papa Rao ,  Noel Russell

    发明人： Stephan Grunow ,  Satyavolu Papa Rao ,  Noel Russell

    IPC分类号： H01L21/768 ,  H05K1/11 ,  H05K3/20

    CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  Y10T29/49128 ,  Y10T29/49165

    摘要： A stacked interconnect structure to connect a first layer copper line with a second layer copper line and method of making the same includes depositing a barrier layer over the inner surfaces of a via extending through a first dielectric layer between the first and second layer copper lines. The first barrier layer provides a barrier to copper diffusion into the dielectric layer. The first barrier layer is then selectively etched from the bottom surface of the via, after which a second barrier layer is deposited over the vertical and bottom surfaces of the via. The second barrier layer also provides a barrier to the diffusion of copper, but is less resistive than the first barrier, and ensure wettability of the copper.

    摘要翻译： 用于将第一层铜线与第二层铜线连接的层叠互连结构及其制造方法包括在穿过第一和第二层铜线之间的第一介电层的通孔的内表面上沉积阻挡层。 第一阻挡层提供对扩散到介电层中的铜的阻挡。 然后从通孔的底表面选择性地蚀刻第一阻挡层，之后在通孔的垂直和底表面上沉积第二阻挡层。 第二阻挡层还提供了对铜的扩散的阻挡，但是比第一屏障具有更小的阻力，并且确保铜的润湿性。