公开(公告)号：US06541280B2

公开(公告)日：2003-04-01

申请号：US09811656

申请日：2001-03-20

申请人： Vidya S. Kaushik ,  Bich-yen Nguyen ,  Srinivas V. Pietambaram ,  James Kenyon Schaeffer, III

发明人： Vidya S. Kaushik ,  Bich-yen Nguyen ,  Srinivas V. Pietambaram ,  James Kenyon Schaeffer, III

IPC分类号： H01L2100

CPC分类号： H01L21/28194 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28 ,  H01L21/28202 ,  H01L21/28273 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A dielectric layer comprises lanthanum, aluminum and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with respect to the lanthanum or aluminum. In another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

摘要翻译： 介电层包括镧，铝和氧，并且形成在两个导体或导体和衬底之间。 在一个实施例中，电介质层相对于镧或铝分级。 在另一个实施例中，在导体或基底与电介质层之间形成绝缘层。 电介质层可以通过原子层化学气相沉积，物理气相沉积，有机金属化学气相沉积或脉冲激光沉积形成。

公开(公告)号：US06518634B1

公开(公告)日：2003-02-11

申请号：US09654704

申请日：2000-09-01

申请人： Vidya S. Kaushik ,  Bich-Yen Nguyen

发明人： Vidya S. Kaushik ,  Bich-Yen Nguyen

IPC分类号： H01L2976

CPC分类号： H01L21/28202 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/318 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming a capacitor and transistor are disclosed. Initially, a substrate having a semiconductor material on a first surface is provided. A layer of strontium nitride is then deposited over the first surface and a gate electrode formed over the strontium nitride. Source and drains are then formed in the first surface disposed laterally adjacent to the gate electrode to leave a channel under the gate electrode. A dielectric layer may be formed over the layer of strontium nitride prior to forming the gate electrode. The dielectric layer may include strontium, titanium, and oxygen. In one embodiment, the dielectric layer and the layer of strontium nitride are epitaxial layers. In another embodiment the layer of strontium nitride is formed by sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD). The dielectric layer may include strontium, oxygen, and nitrogen, such as strontium oxynitride formed by sputtering, CVD, or ALD.

摘要翻译： 公开了形成电容器和晶体管的方法。 首先，设置在第一面上具有半导体材料的基板。 然后在第一表面上沉积一层氮化锶，并在氮化锶上形成一个栅电极。 然后在与栅电极横向相邻设置的第一表面中形成源极和漏极，以在栅电极下方留下通道。 在形成栅电极之前，可以在该氮化锶层之上形成电介质层。 电介质层可以包括锶，钛和氧。 在一个实施例中，介电层和氮化锶层是外延层。 在另一个实施方案中，通过溅射，化学气相沉积（CVD）或原子层沉积（ALD）形成氮化锶层。 电介质层可以包括锶，氧和氮，例如通过溅射，CVD或ALD形成的氧氮化锶。

公开(公告)号：US06184072B2

公开(公告)日：2001-02-06

申请号：US09571588

申请日：2000-05-17

申请人： Vidya S. Kaushik ,  Bich-Yen Nguyen ,  Olubunmi O. Adetutu ,  Christopher C. Hobbs

发明人： Vidya S. Kaushik ,  Bich-Yen Nguyen ,  Olubunmi O. Adetutu ,  Christopher C. Hobbs

IPC分类号： H01L21336

CPC分类号： H01L29/517 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/511 ,  H01L29/518

摘要： A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO2 or a combination of SiO2, SiO3 and SiO4 (oxide-nitride or oxynitride) stacks.

摘要翻译： 处理高K栅极电介质的方法包括在硅界面处生长高质量的二氧化硅层，然后沉积金属层，然后将其扩散到二氧化硅中。 优选的金属包括锆和铪。 可以通过向现有的热生长的SiO 2或SiO 2，SiO 3和SiO 4（氧化物 - 氮化物或氧氮化物）堆叠的组合添加含金属层来制造栅极堆叠。

公开(公告)号：US5712177A

公开(公告)日：1998-01-27

申请号：US533496

申请日：1995-09-25

申请人： Vidya S. Kaushik ,  Hsing-Huang Tseng

发明人： Vidya S. Kaushik ,  Hsing-Huang Tseng

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/51 ,  H01L21/316

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/28273 ,  H01L27/11517 ,  H01L29/513 ,  H01L29/518

摘要： An embodiment of the invention allows the reversing of the sequence of a stacked gate dielectric layer so that a thermal oxide overlies a CVD deposited oxide. A CVD dielectric (12) is first deposited to a desired thickness. Then a layer of silicon (16), either amorphous or polycrystalline, is deposited overlying the CVD dielectric, wherein this silicon layer is approximately one-half of the desired thickness of the final top oxide. The silicon layer is then thermally oxidized to form thermal oxide (18). This method of the invention allows the denser thermal oxide to be formed overlying the less dense CVD dielectric layer as desired to form a reverse dielectric stack.

摘要翻译： 本发明的一个实施例允许堆叠的栅极电介质层的顺序的反转，使得热氧化物覆盖在CVD沉积的氧化物上。 首先将CVD电介质（12）沉积到期望的厚度。 然后沉积覆盖CVD电介质的无定形或多晶硅层（16），其中该硅层约为最终顶部氧化物所需厚度的一半。 然后将硅层热氧化以形成热氧化物（18）。 本发明的这种方法允许根据需要形成覆盖较不致密的CVD电介质层的更致密的热氧化物以形成反向电介质叠层。

公开(公告)号：US06448192B1

公开(公告)日：2002-09-10

申请号：US09835770

申请日：2001-04-16

申请人： Vidya S. Kaushik

发明人： Vidya S. Kaushik

IPC分类号： H01L2131

CPC分类号： H01L21/28194 ,  H01L21/28167 ,  H01L21/28238 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517

摘要： Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.

摘要翻译： 具有多个单层的高质量的氧化硅在硅衬底上在高温下生长。 氧化硅单层是单个硅原子层，每个硅原子键合有两个氧原子。 氧化硅一次蚀刻一个单层，直到获得所需的硅层厚度。 通过引入第一气体以在氧化硅上形成反应层来除去每个单层。 然后清除气体。 然后反应层被另一种气体或热量活化。 然后反应层用于除去单个单层。 重复该过程直到保留所需量的氧化硅层。 因为这种去除方法被限制为一次去除一个单层，所以很好地控制氧化硅的去除。 这允许保留精确量的氧化硅。

公开(公告)号：US5236852A

公开(公告)日：1993-08-17

申请号：US950333

申请日：1992-09-24

申请人： Michael Cherniawski ,  Jeffrey M. Barker ,  Ronald E. Pyle ,  Vidya S. Kaushik

发明人： Michael Cherniawski ,  Jeffrey M. Barker ,  Ronald E. Pyle ,  Vidya S. Kaushik

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S148/019

摘要： An electrical contact (46) to a phosphorous doped polysilicon gate electrode (18) is formed by preventing arsenic, from a source and drain implant, from doping a portion (22) of the polysilicon gate electrode (18). A photoresist mask (20) covers a portion (22) of the polysilicon gate electrode (18) during the implant, thus preventing it from being doped. An electrical contact (46) is then formed to the masked portion (22) of the polysilicon gate electrode (18).

公开(公告)号：US06518106B2

公开(公告)日：2003-02-11

申请号：US09865855

申请日：2001-05-26

申请人： Tat Ngai ,  Bich-Yen Nguyen ,  Vidya S. Kaushik ,  Jamie K. Schaeffer

发明人： Tat Ngai ,  Bich-Yen Nguyen ,  Vidya S. Kaushik ,  Jamie K. Schaeffer

IPC分类号： H01L2100

CPC分类号： H01L21/823842

摘要： A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.