公开(公告)号：US4523368A

公开(公告)日：1985-06-18

申请号：US602280

申请日：1984-04-24

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808 ,  H01L21/265

CPC分类号： H01L29/8086 ,  H01L21/28 ,  H01L29/7832 ,  H01L29/78645 ,  H01L29/78696

摘要： A field effect device having a gate over a portion of a surface of a semiconductor disposed between a source region and a drain region and including a buried doped region having a conductivity type opposite the conductivity type of the semiconductor formed in the semiconductor under, and spaced from such portion of the surface of the semiconductor. The buried doped region is electrically connected to the gate electrode. With such arrangement a field effect device is formed with a connecting channel having a shallow depth in the semiconductor between the gate and the buried doped layer. A method for fabricating field effect devices is also disclosed, such method including the step of forming a pair of masking surfaces of insulating material on the surface of the semiconductor. An ion implantation masking layer is formed between the pair of masking surfaces to enable the selective implantation of particles in the semiconductor to establish the source and drain regions. With such method a single level of masking is used to define the source, drain and gate regions of the device.

摘要翻译： 一种场效应器件，其具有设置在源极区域和漏极区域之间的半导体表面的一部分上的栅极，并且包括具有与在半导体中形成的半导体的导电类型相反的导电类型的掩埋掺杂区域，并且间隔开 从半导体表面的这一部分。 掩埋掺杂区域电连接到栅电极。 通过这样的布置，场效应器件形成有在栅极和掩埋掺杂层之间的半导体中具有浅深度的连接沟道。 还公开了一种用于制造场效应器件的方法，该方法包括在半导体表面上形成一对绝缘材料掩蔽表面的步骤。 在一对掩模表面之间形成离子注入掩模层，以便能够在半导体中选择性地注入颗粒以建立源区和漏区。 使用这种方法，使用单级屏蔽来限定器件的源极，漏极和栅极区域。

公开(公告)号：US4155783A

公开(公告)日：1979-05-22

申请号：US903433

申请日：1978-05-08

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/822 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L27/04 ,  H01L21/302 ,  H01L21/20 ,  H01L27/12

CPC分类号： H01L21/764 ,  H01L21/76 ,  H01L21/7621 ,  H01L21/76216

摘要： Semiconductor integrated circuit structures and manufacturing methods wherein isolation grooves are etched into a semiconductor body by first bringing an anisotropic etchant in contact with portions of the surface of the body which are exposed by windows formed in an etch-resistant mask to form grooves with side walls which intersect the surface at acute angles. Next, an isotropic etchant is brought in contact with the walls of the etched grooves to remove portions of the body which are underneath the etch-resistant mask such that the mask extends over the side walls of the resulting grooves, the bottom walls of such grooves are disposed under the windows and the side walls maintain acute angle intersection with the surface. Junction isolation regions are formed by ion implanting particles into the bottom walls of the grooves, the maks shielding the side walls from such particles. This self-aligning process accurately controls the placement of the junction isolation regions and thereby reduces the depth required for the grooves in providing dielectric isolation. Because the grooves have side walls which intersect the surface at acute angles, and because the grooves are relatively shallow because of the addition of accurately placed junction isolation regions, subsequent metallization processing is more readily controllable.

摘要翻译： 半导体集成电路结构和制造方法，其中通过首先使各向异性蚀刻剂与由形成在耐蚀刻掩模中的窗户露出的主体表面的部分接触形成半导体主体，以形成具有侧壁的凹槽 其以锐角与表面相交。 接下来，使各向同性蚀刻剂与蚀刻槽的壁接触以去除抗蚀剂掩模下方的主体部分，使得掩模在所得到的凹槽的侧壁上延伸，这些凹槽的底壁 设置在窗户下方，侧壁与表面保持锐角交叉。 通过将离子注入到槽的底壁中的方式形成结隔离区域，maks将侧壁与这些颗粒隔离。 该自对准过程精确地控制结隔离区域的布置，从而减少沟槽提供电介质隔离所需的深度。 因为凹槽具有以锐角与表面相交的侧壁，并且由于添加精确放置的结隔离区，因为沟槽相对较浅，所以随后的金属化处理更易于控制。

公开(公告)号：US4933295A

公开(公告)日：1990-06-12

申请号：US289517

申请日：1988-12-27

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/665 ,  H01L29/732 ,  Y10S148/01 ,  Y10S148/011

摘要： A method of forming a bipolar transistor comprising the steps of forming a base region in a semiconductor structure and disposing an emitter region on a surface of a first portion of the base region, the emitter region having upper and side surfaces. An active base region is formed in the first portion of the base region and an inactive base region is formed in a second portion of the base region adjacent to the first portion and the side surface of the emitter region. A layer of insulating material is formed over a surface of the inactive base region and over the upper and side surfaces of the emitter region. Portions of such layer are selectively removed to expose the upper surface of the emitter region and a portion of the surface of the inactive base region, and to maintain a region of insulating material between the exposed surface portion of the inactive base region and the side surface of the emitter region. Silicide contacts are formed on the exposed surface portion of the inactive base region and the exposed upper surface of the emitter region, with the insulating material region insulating such contacts from each other. With such arrangement, the spacing between the base and emitter contacts may be substantially reduced, such as to the width of the insulating material region, thereby reducing the size (i.e. width), base-to-emitter resistance, base contact resistance and base-to-emitter and base-to-collector capacitance of the bipolar transistor.

摘要翻译： 一种形成双极晶体管的方法，包括以下步骤：在半导体结构中形成基极区域，并在基极区域的第一部分的表面上设置发射极区域，发射极区域具有上表面和侧表面。 在基极区域的第一部分中形成有源基极区域，并且在与发射极区域的第一部分和侧表面相邻的基极区域的第二部分中形成非活性基极区域。 绝缘材料层形成在非活性碱性区域的表面上，并且在发射极区域的上表面和侧表面上。 选择性地去除这样的层的一部分以暴露发射极区域的上表面和非活性碱性区域的表面的一部分，并且在非活性碱性区域的暴露表面部分和侧表面之间保持绝缘材料区域 的发射极区域。 在非活性碱性区域的暴露表面部分和发射区域的暴露的上表面上形成硅化物接触，绝缘材料区域使这种接触彼此绝缘。 通过这种布置，基极和发射极触点之间的间隔可以基本上减小，例如到绝缘材料区域的宽度，从而减小尺寸（即宽度），基极 - 发射极电阻，基极接触电阻和基极 - 双极晶体管的发射极和基极到集电极电容。

公开(公告)号：US4402761A

公开(公告)日：1983-09-06

申请号：US342861

申请日：1982-01-26

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/033 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/302 ,  H01L21/26

CPC分类号： H01L29/7835 ,  H01L21/033 ,  H01L29/1033 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659

摘要： A semiconductor structure wherein a masking layer is formed to cover a portion of a surface of a semiconductor. A first doped region is formed in a portion of the semiconductor exposed by the masking layer. A chemical etchant is brought into contact with the masking layer, reducing the area of the masking layer covering the semiconductor exposing a second, different portion of the semiconductor contiguous to the first exposed portion of the semicoductor. Particles capable of establishing a doped region in the semiconductor layer are introduced into the second, different exposed portion of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, such chemically etched masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self-aligned gate region may be formed in a field effect device having small channel lengths.

摘要翻译： 一种半导体结构，其中形成掩模层以覆盖半导体表面的一部分。 第一掺杂区域形成在被掩模层暴露的半导体的一部分中。 使化学蚀刻剂与掩模层接触，减少覆盖半导体的掩模层的面积，暴露与半导体的第一暴露部分邻接的半导体的第二不同部分。 能够在半导体层中建立掺杂区域的粒子被引入到半导体的第二不同的暴露部分中，以在与第一掺杂区域邻接的半导体中形成第二掺杂区域，这种化学蚀刻掩模层抑制这种颗粒的引入 进入设置在化学蚀刻掩模层下方的半导体部分。 利用这种方法，可以在具有小通道长度的场效应器件中形成自对准栅极区域。

公开(公告)号：US4216574A

公开(公告)日：1980-08-12

申请号：US920594

申请日：1978-06-29

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L29/762 ,  H01L21/339 ,  H01L29/10 ,  H01L29/768 ,  B01J17/00

CPC分类号： H01L29/76841 ,  H01L29/1062

摘要： A two-phase buried-channel charge coupled device wherein a doped layer of first type conductivity is formed with a predetermined doping concentration under a surface of a semiconductor body of second type conductivity. A first plurality of electrodes is formed in spaced relationship on the surface over the doped layer. Particles generating the first type conductivity are ion implanted into regions of the doped layer between the first plurality of electrodes, increasing the doping concentration of the portion of the doped layer disposed beneath such spaced regions. A second plurality of electrodes is formed over the increased concentration portions of the doped layer. The first plurality of electrodes provides the transfer gates of the device and the second plurality of electrodes provides the storage gates for the device.

摘要翻译： 一种二相掩埋沟道电荷耦合器件，其中在第二导电类型的半导体本体的表面下形成具有预定掺杂浓度的第一类型导电性的掺杂层。 在掺杂层上的表面上以间隔的关系形成第一多个电极。 产生第一类型电导率的颗粒被离子注入到第一多个电极之间的掺杂层的区域中，增加了设置在这种间隔区域之下的掺杂层的部分的掺杂浓度。 在掺杂层的增加的浓度部分上形成第二多个电极。 第一多个电极提供器件的传输门，并且第二多个电极为器件提供存储门。

公开(公告)号：US3983574A

公开(公告)日：1976-09-28

申请号：US553717

申请日：1975-02-27

申请人： Hermann Statz ,  Wolfgang M. Feist

发明人： Hermann Statz ,  Wolfgang M. Feist

IPC分类号： H01J29/45 ,  H01L21/00 ,  H01L21/3115 ,  H01L27/00 ,  H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L31/00 ,  H01L31/0216 ,  H01L27/14

CPC分类号： H01L31/02161 ,  H01J29/451 ,  H01J29/455 ,  H01J9/233 ,  H01L21/00 ,  H01L21/31155 ,  H01L27/00 ,  H01L29/00 ,  H01L29/0638 ,  H01L29/78 ,  H01L31/00 ,  H01L31/0216 ,  Y10S257/917

摘要： A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in a non-blooming vidicon. The method of manufacturing such a structure uses ion implantation to create immobile positive charges in a grid pattern in an insulating layer in regions spaced from the interface between the insulating layer and the semiconductor body. The insulating layer is of sufficient thickness that substantially all of the charge sites in the insulating layer are separated from the outer surface of the insulator by a sufficient distance to effectively prevent a negative electric field from reaching into the silicon.

摘要翻译： 具有表面绝缘层的半导体结构，其形成为栅格，电荷注入绝缘材料中，以防止反转，并因此在相邻半导体区之间引导沟道，优选用于非开花的视频体。 制造这种结构的方法使用离子注入来在与绝缘层和半导体本体之间的界面间隔开的区域中的绝缘层中以栅格图案形成固定的正电荷。 绝缘层具有足够的厚度，绝缘层中的基本上所有的电荷位置与绝缘体的外表面分开足够的距离，以有效地防止负电场进入硅。

公开(公告)号：US3979629A

公开(公告)日：1976-09-07

申请号：US547161

申请日：1975-02-05

申请人： Hermann Statz ,  Wolfgang M. Feist

发明人： Hermann Statz ,  Wolfgang M. Feist

IPC分类号： H01J29/45 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L31/00 ,  H01L31/0216 ,  H01J31/38

CPC分类号： H01L31/0216 ,  H01J29/455 ,  H01J9/233 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/0611 ,  H01L29/78 ,  H01L31/00

摘要： A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in a nonblooming vidicon. The method of manufacturing such a structure uses ion implantation to create immobile positive charges in a grid pattern in an insulating layer in regions spaced from the interface between the insulating layer and the semiconductor body. The insulating layer is of sufficient thickness that substantially all of the charge sites in the insulating layer are separated from the outer surface of the insulator by a sufficient distance to effectively prevent a negative electric field from reaching into the silicon.

摘要翻译： 具有表面绝缘层的半导体结构，其表面电荷形成为栅极，电荷注入到绝缘材料中以防止反转，并因此在相邻的半导体区域之间引导沟道，优选用于不起眼的摄像机。 制造这种结构的方法使用离子注入来在与绝缘层和半导体本体之间的界面间隔开的区域中的绝缘层中以栅格图案形成固定的正电荷。 绝缘层具有足够的厚度，绝缘层中的基本上所有的电荷位置与绝缘体的外表面分开足够的距离，以有效地防止负电场进入硅。

公开(公告)号：US3960562A

公开(公告)日：1976-06-01

申请号：US419302

申请日：1973-11-27

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01J29/39 ,  H01J31/48

CPC分类号： H01J9/233 ,  H01J29/395

摘要： A membrane type dielectric storage target formed from a thin refractory dielectric film is stretched to form at least a one-sided surface, a first surface portion contacting a conductive wire mesh, a second surface portion having areas coated with conductive material imaging the mesh of the first surface portion. The method contemplates forming the conductive image on the second surface portion by photo-resist, decoration, and breakdown techniques.

摘要翻译： 由薄耐火介电膜形成的膜型电介质存储靶被拉伸以形成至少单面表面，与导电丝网接触的第一表面部分，具有涂覆有导电材料的区域的第二表面部分， 第一表面部分。 该方法考虑通过光刻胶，装饰和击穿技术在第二表面部分上形成导电图像。

公开(公告)号：US5064773A

公开(公告)日：1991-11-12

申请号：US373306

申请日：1989-06-29

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L29/73 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/47 ,  H01L29/732 ,  H01L29/872

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/01 ,  Y10S148/019

摘要： A method of forming a bipolar transistor. A base region is implanted into an epitaxial layer. An emitter and collector contact regions are formed of doped polysilicon on the epitaxial layer, the emitter being formed over the base region. The implant is below the surface of the epitaxial layer in all regions not covered by the collector region. Low resistance silicide contacts, such as titanium or cobalt, are formed on the structure in a self-aligned fashion. This method is well suited for forming BJTs as part of BiCMOS circuits.

摘要翻译： 一种形成双极晶体管的方法。 将基极区植入到外延层中。 发射极和集电极接触区域由外延层上的掺杂多晶硅形成，发射极形成在基极区域上。 植入物在未被收集器区域覆盖的所有区域中在外延层的表面之下。 在自对准方式的结构上形成低电阻硅化物触点，例如钛或钴。 该方法非常适合作为BiCMOS电路的一部分形成BJT。

公开(公告)号：US4289550A

公开(公告)日：1981-09-15

申请号：US42686

申请日：1979-05-25

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/8222 ,  H01L21/306 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L27/06 ,  H01L29/10 ,  H01L29/73 ,  H01L29/737 ,  H01L21/20 ,  H01L21/302

CPC分类号： H01L29/1004 ,  H01L21/7621 ,  H01L21/76216 ,  H01L29/7375 ,  Y10S148/051 ,  Y10S148/106 ,  Y10S148/168

摘要： A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer. A doped polycrystalline silicon layer is formed over the bottom portion of the depression in contact with the active base region to provide an emitter contact for the transistor.

摘要翻译： 通过在半导体层的一部分中形成隔离区域形成半导体结构，在邻近隔离区域的半导体层中形成掺杂区域，该掺杂区域具有与半导体层的导电类型相反的导电类型， 所述半导体层的表面暴露出与所述隔离区相邻的所述掺杂区的一部分，并且选择性地蚀刻所述相邻掺杂区的所述暴露部分，形成具有所述掺杂区域的一部分与所述隔离区隔开的会聚侧壁的凹陷。 半导体层是提供晶体管的集电极区域的外延层。 凹陷的底部被轻掺杂以提供晶体管的有源基极区域。 有源基区通过形成在半导体层中的更高掺杂区电连接到基极接触。 掺杂多晶硅层形成在与有源基极区接触的凹陷的底部上，以提供晶体管的发射极接触。