公开(公告)号：US20190129651A1

公开(公告)日：2019-05-02

申请号：US15794457

申请日：2017-10-26

申请人： ADVANCED MICRO DEVICES, INC.

发明人： John WUU ,  Michael K. CIRAULA ,  Russell SCHREIBER ,  Samuel NAFFZIGER

IPC分类号： G06F3/06 ,  G06F12/1009

摘要： A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.

公开(公告)号：US20240234304A1

公开(公告)日：2024-07-11

申请号：US18402688

申请日：2024-01-02

申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

发明人： Deepak Vasant KULKARNI ,  Samuel NAFFZIGER ,  Raja SWAMINATHAN ,  Matthew STRAAYER ,  Justin Michael BURKHART ,  Sri Ranga Sai BOYAPATI ,  Hemanth Kumar DHAVALESWARAPU ,  Alexander Helmut PFEIFFENBERGER ,  Manjunath D. HARITSA

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5227 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/29 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/15311

摘要： Chip packages are described herein that includes chiplets embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. In one example, the chiplet includes voltage regulation circuitry that is coupled through a substrate core embedded inductor to an integrated circuit (IC) die mounted to the substrate.

公开(公告)号：US20240330196A1

公开(公告)日：2024-10-03

申请号：US18388602

申请日：2023-11-10

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Skyler J. SALEH ,  Samuel NAFFZIGER ,  Milind S. BHAGAVAT ,  Rahul AGARWAL

IPC分类号： G06F12/0897 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F12/0897 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2212/1024

摘要： A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.