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    Integrity monitoring for flexible material
    1.
    发明授权
    Integrity monitoring for flexible material 有权

    公开(公告)号：US11969030B2

    公开(公告)日：2024-04-30

    申请号：US17543070

    申请日：2021-12-06

    Applicant: Arm Limited

    Inventor： Emre Ozer ,  Jedrzej Kufel ,  James Edward Myers ,  Remy Pottier ,  John Philip Biggs

    IPC: A41D1/00 ,  A41D19/015 ,  A61F6/04 ,  G01R31/28

    CPC classification number: A41D1/002 ,  A41D19/015 ,  A61F6/04 ,  G01R31/2812

    Abstract: Wearable items and methods of monitoring wearable items are disclosed. The wearable item comprises a flexible base material forming at least a portion of the wearable item, plural conductive traces traversing the flexible base material, and conductivity sensing circuitry coupled to the plural conductive traces. The conductivity sensing circuitry is configured to distinguish conductivity from non-conductivity of the plural conductive traces, and configured to generate a conductivity indication for at least one of the plural conductive traces. The plural conductive traces follow indirect paths across the flexible base material, allowing the flexible material to flex and stretch normally without breaking the conductive traces.

    System-in-package architecture with wireless bus interconnect
    3.
    发明授权
    System-in-package architecture with wireless bus interconnect 有权

    公开(公告)号：US11366779B2

    公开(公告)日：2022-06-21

    申请号：US16685090

    申请日：2019-11-15

    Applicant: Arm Limited ,  ECS Partners Limited

    Inventor： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Terrence Sui Tung Mak

    IPC: G06F13/40 ,  H04L12/40

    Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

    Periphery Body Biasing for Memory Applications
    5.
    发明申请
    Periphery Body Biasing for Memory Applications 审中-公开

    公开(公告)号：US20190304962A1

    公开(公告)日：2019-10-03

    申请号：US15942132

    申请日：2018-03-30

    Applicant: Arm Limited

    Inventor： Pranay Prabhat ,  James Edward Myers

    IPC: H01L27/02 ,  G11C11/412 ,  G11C11/417

    Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.

    Flip-Flop
    7.
    发明申请
    Flip-Flop 有权

    公开(公告)号：US20180123571A1

    公开(公告)日：2018-05-03

    申请号：US15336721

    申请日：2016-10-27

    Applicant: ARM Limited ,  University of Southampton

    Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

    IPC: H03K3/3562 ,  H03K19/20

    CPC classification number: H03K3/35625 ,  H03K19/20

    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

    Controlling voltage generation and voltage comparison
    9.
    发明授权
    Controlling voltage generation and voltage comparison 有权

    公开(公告)号：US09496785B2

    公开(公告)日：2016-11-15

    申请号：US14922783

    申请日：2015-10-26

    Applicant: ARM Limited

    Inventor： Parameshwarappa Anand Kumar Savanth ,  James Edward Myers ,  David Walter Flynn ,  Bal S. Sandhu

    IPC: G01R35/06 ,  H02M3/157 ,  G01R19/00 ,  H02M3/07

    CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

    Devices and methods to store an initialization state
    10.
    发明授权
    Devices and methods to store an initialization state 有权

    公开(公告)号：US11200940B2

    公开(公告)日：2021-12-14

    申请号：US16683192

    申请日：2019-11-13

    Applicant: Arm Limited

    Inventor： Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight

    IPC: G11C7/02 ,  G11C11/4072 ,  G11C11/408 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4094

    Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.

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