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14 条记录 (耗时 0.017 秒)

    Voltage droop mitigation in 3D chip system
    2.
    发明授权
    Voltage droop mitigation in 3D chip system 有权
    3D芯片系统中降压降压

    公开(公告)号：US09595508B2

    公开(公告)日：2017-03-14

    申请号：US14144920

    申请日：2013-12-31

    申请人： Advanced Micro Devices, Inc.

    发明人： Yi Xu ,  Xing Hu ,  Yuan Xie

    IPC分类号： G06F17/50 ,  H01L25/07 ,  G06F1/32

    CPC分类号： H01L25/074 ,  G06F1/329 ,  G06F9/4881 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  Y02D10/24 ,  H01L2924/00

    摘要： The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

    摘要翻译： 本发明涉及一种多芯片系统和一种在3D堆叠芯片中调度线程的方法。 多芯片系统包括垂直堆叠并电耦合在一起的多个管芯; 所述多个模具中的每一个包括一个或多个芯，所述多个模具中的每一个还包括：至少一个电压违规感测单元，所述至少一个电压违规感测单元与每个裸片的所述一个或多个芯相连接， 至少一个电压感测单元被配置为独立地感测每个管芯的每个铁芯中的电压违例; 以及至少一个频率调谐单元，所述至少一个频率调谐单元经配置以调谐每个芯片的每个芯片的频率，所述至少一个频率调谐单元与所述至少一个电压违规感测单元连接。 本发明中描述的多芯片系统和方法具有许多优点，例如减少电压冲击，降低电压下降和节省功率。

    THERMAL-AWARE COMPILER FOR PARALLEL INSTRUCTION EXECUTION IN PROCESSORS
    3.
    发明申请
    THERMAL-AWARE COMPILER FOR PARALLEL INSTRUCTION EXECUTION IN PROCESSORS 有权
    用于并行执行处理器的热备份编译器

    公开(公告)号：US20160098275A1

    公开(公告)日：2016-04-07

    申请号：US13976905

    申请日：2013-05-21

    申请人： Advanced Micro Devices, Inc.

    发明人： Yuan Xie ,  Junli Gu

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30083 ,  G06F8/4432 ,  G06F9/30087 ,  G06F9/30149 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D10/41

    摘要： Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.

    摘要翻译： 描述了一种用于通过确定处理器的热约束来编译在具有多个功能单元的处理器中执行的指令代码的方法的实施例，并且将包括实际指令和一个或多个无操作（NOP）指令的指令字定义为 在单个时钟周期内由功能单元执行，其中在多个连续时钟周期执行的多个NOP指令被配置为在执行指令代码期间防止超过热约束。

    MOVING DATA BETWEEN CACHES IN A HETEROGENEOUS PROCESSOR SYSTEM
    4.
    发明申请
    MOVING DATA BETWEEN CACHES IN A HETEROGENEOUS PROCESSOR SYSTEM 有权
    移动异步处理器系统中的缓存之间的数据

    公开(公告)号：US20160041909A1

    公开(公告)日：2016-02-11

    申请号：US14452058

    申请日：2014-08-05

    申请人： Advanced Micro Devices, Inc.

    发明人： JunLi Gu ,  Bradford M. Beckmann ,  Yuan Xie

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0813 ,  G06F12/0811 ,  G06F12/0835 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/507

    摘要： Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at least on the stored information to move the plurality of data items to the second cache. The method includes moving the plurality of data items to the second cache. The method may include determining a time interval between receiving the indication that the first cache requested the plurality of data items and moving the plurality of data items to the second cache. A scratch pad memory is disclosed.

    摘要翻译： 呈现装置，计算机可读介质，集成电路和将多个数据项移动到第一高速缓存或第二高速缓存的方法。 该方法包括接收第一缓存请求多个数据项的指示。 所述方法包括存储指示所述第一高速缓存请求所述多个数据项的信息。 该信息可以包括多个数据项中的每一个的地址。 该方法包括至少基于存储的信息确定以将多个数据项移动到第二高速缓存。 该方法包括将多个数据项移动到第二高速缓存。 所述方法可以包括确定在接收到所述第一高速缓存请求所述多个数据项之间并且将所述多个数据项移动到所述第二高速缓存的指示之间的时间间隔。 公开了一种临时存储器。

    VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM
    5.
    发明申请
    VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM 有权
    三维芯片系统中的电压降低

    公开(公告)号：US20150160975A1

    公开(公告)日：2015-06-11

    申请号：US14144920

    申请日：2013-12-31

    申请人： Advanced Micro Devices, Inc.

    发明人： Yi Xu ,  Xing Hu ,  Yuan Xie

    IPC分类号： G06F9/48 ,  G05F1/46 ,  H01L25/07

    CPC分类号： H01L25/074 ,  G06F1/329 ,  G06F9/4881 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  Y02D10/24 ,  H01L2924/00

    摘要： The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

    摘要翻译： 本发明涉及一种多芯片系统和一种在3D堆叠芯片中调度线程的方法。 多芯片系统包括垂直堆叠并电耦合在一起的多个管芯; 所述多个模具中的每一个包括一个或多个芯，所述多个模具中的每一个还包括：至少一个电压违规感测单元，所述至少一个电压违规感测单元与每个裸片的所述一个或多个芯相连接， 至少一个电压感测单元被配置为独立地感测每个管芯的每个铁芯中的电压违例; 以及至少一个频率调谐单元，所述至少一个频率调谐单元经配置以调谐每个芯片的每个芯片的频率，所述至少一个频率调谐单元与所述至少一个电压违规感测单元连接。 本发明中描述的多芯片系统和方法具有许多优点，例如减少电压冲击，降低电压下降和节省功率。

    Memory system with region-specific memory access scheduling
    6.
    发明授权
    Memory system with region-specific memory access scheduling 有权

    公开(公告)号：US10956044B2

    公开(公告)日：2021-03-23

    申请号：US14891523

    申请日：2013-05-16

    申请人： Advanced Micro Devices, Inc.

    发明人： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

    IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G06F1/3203 ,  G11C7/10

    摘要： An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

    Voltage droop mitigation in 3D chip system
    7.
    发明授权
    Voltage droop mitigation in 3D chip system 有权

    公开(公告)号：US10361175B2

    公开(公告)日：2019-07-23

    申请号：US15428536

    申请日：2017-02-09

    申请人： Advanced Micro Devices, Inc.

    发明人： Yi Xu ,  Xing Hu ,  Yuan Xie

    IPC分类号： G06F17/50 ,  H01L25/07 ,  G06F1/329 ,  G06F9/48 ,  H01L25/065 ,  H01L23/528

    摘要： The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

    Enhancing Lifetime of Non-Volatile Cache by Injecting Random Replacement Policy
    9.
    发明申请
    Enhancing Lifetime of Non-Volatile Cache by Injecting Random Replacement Policy 有权
    通过注入随机替代策略来增强非易失性缓存的使用寿命

    公开(公告)号：US20150100739A1

    公开(公告)日：2015-04-09

    申请号：US14229404

    申请日：2014-03-28

    申请人： Advanced Micro Devices, Inc.

    发明人： Zhe WANG ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/127 ,  G06F12/121 ,  G06F2212/222

    摘要： A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.

    摘要翻译： 提供了用于写入非易失性高速缓冲存储器的方法，系统和计算机可读介质。 该方法保持与一组存储器位置相关联的写入计数。 然后，该方法基于写入计数的值来选择高速缓存替换策略，并且使用所选择的高速缓存替换策略来选择用于写入数据的集合内的块。 所选择的高速缓存替换策略可以引入随机选择。