公开(公告)号：US20170133311A1

公开(公告)日：2017-05-11

申请号：US15410688

申请日：2017-01-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Li KAO ,  Chang-Chi LEE ,  Yi-Shao LAI

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/15738 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15798 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2224/0401

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

公开(公告)号：US20160211235A1

公开(公告)日：2016-07-21

申请号：US14599366

申请日：2015-01-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long CHEN ,  Ping-Feng YANG ,  Chang-Chi LEE ,  Chien-Fan CHEN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0614 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1414 ,  H01L2224/16055 ,  H01L2224/16056 ,  H01L2224/81191 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

Abstract translation: 本公开涉及凸块结构以及具有该凸块结构的半导体器件和半导体器件封装。 半导体器件包括主体，至少一个导电金属焊盘和至少一个金属支柱。 身体包括第一表面。 至少一个导电金属垫设置在第一表面上。 每个金属柱形成在相应的导电金属垫上。 每个金属柱具有与第一凹入侧壁相对的凹侧壁和凸侧壁，并且凹侧壁和凸侧壁与相应的导电金属垫正交。

公开(公告)号：US20140332957A1

公开(公告)日：2014-11-13

申请号：US14274289

申请日：2014-05-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Li KAO ,  Chang-Chi LEE ,  Yi-Shao LAI

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/15738 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15798 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2224/0401

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Abstract translation: 本发明涉及半导体封装及其制造方法。半导体封装包括半导体元件，其包括主体，多个导电通孔和至少一个填充物。 导电通孔穿过主体。 填料位于主体中，填料的热膨胀系数（CTE）与主体和导电通孔的热膨胀系数不同。 因此，可以调整整个半导体元件的CTE，以便减少翘曲。