公开(公告)号：US08937387B2

公开(公告)日：2015-01-20

申请号：US13671409

申请日：2012-11-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Che-Hau Huang ,  Ying-Te Ou

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05681 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/83385 ,  H01L2224/85005 ,  H01L2224/85205 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.

Abstract translation: 本公开涉及具有导电通孔的半导体器件。 在一个实施例中，半导体器件包括其中形成有至少一个导电通孔的衬底。 导电通孔具有与基板的非活性表面基本上共面的第一端。 电路层设置成与衬底的有源表面相邻并且电连接到导电通孔的第二端。 再分配层邻近基板的非活性表面设置，再分配层具有设置在第一端上的电连接到其上的第一部分和位于上方并远离第一部分的第二部分。 模具靠近基板的非活性表面设置并电连接到再分布层的第二部分。

公开(公告)号：US10472228B2

公开(公告)日：2019-11-12

申请号：US15680056

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Cheng-Yuan Kung ,  Che-Hau Huang ,  Chin-Cheng Kuo

IPC: B81B7/00 ,  B81C1/00 ,  H03H9/64 ,  H03H9/54 ,  H03H9/05

Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.