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公开(公告)号：US20060275981A1
公开(公告)日：2006-12-07
申请号：US11442602
申请日：2006-05-30
申请人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
发明人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/10867
摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.
摘要翻译： 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。
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公开(公告)号：US20050181557A1
公开(公告)日：2005-08-18
申请号：US11040091
申请日：2005-01-24
申请人： Stefan Jakschik , Thomas Hecht , Uwe Schroder , Matthias Goldbach
发明人： Stefan Jakschik , Thomas Hecht , Uwe Schroder , Matthias Goldbach
IPC分类号： H01L21/20 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/334 , H01L21/8242
CPC分类号： H01L27/1087 , H01L21/31111 , H01L21/3141 , H01L21/31616 , H01L29/66181
摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.
摘要翻译： 用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。 然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。 最后，再次选择性地除去氧化铝，例如使用热磷酸。 由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。
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公开(公告)号：US20050003642A1
公开(公告)日：2005-01-06
申请号：US10835259
申请日：2004-04-30
申请人： Thomas Hecht , Uwe Schroder , Ulrich Mantz , Stefan Jakschik , Andreas Orth
发明人： Thomas Hecht , Uwe Schroder , Ulrich Mantz , Stefan Jakschik , Andreas Orth
IPC分类号： G01B11/22 , G01J3/453 , G01N21/21 , H01L21/337
CPC分类号： G01N21/211 , G01B11/22 , G01J3/453
摘要： The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer behavior of the semiconductor wafer which is brought about by the buried structure when the semiconductor wafer is irradiated with electromagnetic radiation in the infrared range and arises as a result of the significantly longer wavelengths of the radiation used in comparison with the lateral dimensions of the buried structure is utilized to determine the depth of the buried structure by spectrometric and/or ellipsometric methods.
摘要翻译： 本发明涉及一种用于确定半导体晶片中的掩埋结构的深度的方法。 根据本发明，当半导体晶片在红外范围内被电磁辐射照射时，由掩埋结构引起的半导体晶片的层行为，并且由于与所使用的辐射相比显着更长的辐射波长而产生 掩埋结构的横向尺寸用于通过光谱测量和/或椭偏方法确定掩埋结构的深度。
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公开(公告)号：US20060234463A1
公开(公告)日：2006-10-19
申请号：US11399811
申请日：2006-04-07
IPC分类号： H01L21/20 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： H01L28/65 , H01L27/1087 , H01L29/66181
摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。
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5.发明申请公开(公告)号：US20060202250A1
公开(公告)日：2006-09-14
申请号：US11076021
申请日：2005-03-10
IPC分类号： H01L29/94
CPC分类号： H01L27/10852 , H01L27/0207 , H01L28/82
摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.
摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。
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公开(公告)号：US20080242097A1
公开(公告)日：2008-10-02
申请号：US11729360
申请日：2007-03-28
申请人： Tim Boescke , Annette Saenger , Stefan Jakschik , Christian Fachmann , Matthias Patz , Alejandro Avellan , Thomas Hecht , Jonas Sundqvist
发明人： Tim Boescke , Annette Saenger , Stefan Jakschik , Christian Fachmann , Matthias Patz , Alejandro Avellan , Thomas Hecht , Jonas Sundqvist
CPC分类号： H01L29/945 , C30B25/04 , H01L21/02148 , H01L21/02159 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/31612 , H01L21/31616 , H01L21/31645
摘要： The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.
摘要翻译： 本发明涉及选择性沉积方法。 提供了包括至少一个结构化表面的衬底。 结构化表面包括第一区域和第二区域。 对于第一沉积技术的反应物，第一区域被选择性地钝化，并且第二区域被激活关于第一沉积技术的反应物。 通过第一沉积技术沉积第二区域上的钝化层。 对于选自一组氧化反应物的前体，钝化层是惰性的。 使用第二原子层沉积技术将层沉积在第二区域中，作为使用从氧化反应物组中选择的前体的第二沉积技术。
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公开(公告)号：US07531406B2
公开(公告)日：2009-05-12
申请号：US11399811
申请日：2006-04-07
IPC分类号： H01L21/8234
CPC分类号： H01L28/65 , H01L27/1087 , H01L29/66181
摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。
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公开(公告)号：US20060134871A1
公开(公告)日：2006-06-22
申请号：US11017194
申请日：2004-12-20
IPC分类号： H01L21/336
CPC分类号： H01L29/512 , H01L21/28282 , H01L29/42348 , H01L29/78 , H01L29/7923
摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.
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公开(公告)号：US07268037B2
公开(公告)日：2007-09-11
申请号：US11040091
申请日：2005-01-24
申请人： Stefan Jakschik , Thomas Hecht , Uwe Schröder , Matthias Goldbach
发明人： Stefan Jakschik , Thomas Hecht , Uwe Schröder , Matthias Goldbach
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/31111 , H01L21/3141 , H01L21/31616 , H01L29/66181
摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.
摘要翻译： 用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。 然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。 最后，再次选择性地除去氧化铝，例如使用热磷酸。 由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。
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公开(公告)号：US07132337B2
公开(公告)日：2006-11-07
申请号：US11017194
申请日：2004-12-20
IPC分类号： H01L21/336
CPC分类号： H01L29/512 , H01L21/28282 , H01L29/42348 , H01L29/78 , H01L29/7923
摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.
摘要翻译： 电荷捕获区域布置在栅电极的下边缘下方彼此分离。 源极/漏极区域以相对于电荷俘获区域的自对准方式通过在低能量下的掺杂工艺形成，以形成仅在电荷俘获区域下方仅小的距离的浅结。 自对准确保了大量的编程擦除周期，具有高效率和良好的数据保留，因为注入相反符号的电荷载体的位置被狭义地和精确地定义。
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