公开(公告)号：US20060275981A1

公开(公告)日：2006-12-07

申请号：US11442602

申请日：2006-05-30

申请人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

发明人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10867

摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

摘要翻译： 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。

公开(公告)号：US20050181557A1

公开(公告)日：2005-08-18

申请号：US11040091

申请日：2005-01-24

申请人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schroder ,  Matthias Goldbach

发明人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schroder ,  Matthias Goldbach

IPC分类号： H01L21/20 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  H01L21/31111 ,  H01L21/3141 ,  H01L21/31616 ,  H01L29/66181

摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

摘要翻译： 用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。 然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。 最后，再次选择性地除去氧化铝，例如使用热磷酸。 由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。

公开(公告)号：US20060134871A1

公开(公告)日：2006-06-22

申请号：US11017194

申请日：2004-12-20

申请人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

发明人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

IPC分类号： H01L21/336

CPC分类号： H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

公开(公告)号：US07268037B2

公开(公告)日：2007-09-11

申请号：US11040091

申请日：2005-01-24

申请人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schröder ,  Matthias Goldbach

发明人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schröder ,  Matthias Goldbach

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L21/31111 ,  H01L21/3141 ,  H01L21/31616 ,  H01L29/66181

摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

摘要翻译： 用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。 然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。 最后，再次选择性地除去氧化铝，例如使用热磷酸。 由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。

公开(公告)号：US07132337B2

公开(公告)日：2006-11-07

申请号：US11017194

申请日：2004-12-20

申请人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

发明人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

IPC分类号： H01L21/336

CPC分类号： H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

摘要翻译： 电荷捕获区域布置在栅电极的下边缘下方彼此分离。 源极/漏极区域以相对于电荷俘获区域的自对准方式通过在低能量下的掺杂工艺形成，以形成仅在电荷俘获区域下方仅小的距离的浅结。 自对准确保了大量的编程擦除周期，具有高效率和良好的数据保留，因为注入相反符号的电荷载体的位置被狭义地和精确地定义。

公开(公告)号：US20050277295A1

公开(公告)日：2005-12-15

申请号：US11147892

申请日：2005-06-08

申请人： Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroder

发明人： Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroder

IPC分类号： C23C14/04 ,  C23C16/02 ,  C23C16/04 ,  C23C16/40 ,  H01L21/20 ,  H01L21/283 ,  H01L21/285 ,  H01L21/31 ,  H01L21/314 ,  H01L21/44 ,  H01L21/469 ,  H01L21/66 ,  H01L21/762 ,  H01L21/768

CPC分类号： C23C16/0281 ,  C23C14/046 ,  C23C16/045 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/76877 ,  H01L22/26

摘要： The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).

摘要翻译： 本发明提供一种用于图案化衬底表面的涂覆方法，其中提供衬底（101），该衬底具有在衬底图案化区域（102）中被图案化并具有一个或多个沟槽（106）的表面（105） 将其填充到预定的填充高度（205），将催化剂层（201）引入要填充的沟槽（106）中，在沟槽（106）中催化沉积反应层（202），其中 要填充的催化沉积反应层（202）在要填充的沟槽（106）中致密化，并且重复引入催化剂层（201）和催化沉积反应层（202） 直到要填充的沟槽（106）已经被填充到预定填充高度（205）。

公开(公告)号：US20050003642A1

公开(公告)日：2005-01-06

申请号：US10835259

申请日：2004-04-30

申请人： Thomas Hecht ,  Uwe Schroder ,  Ulrich Mantz ,  Stefan Jakschik ,  Andreas Orth

发明人： Thomas Hecht ,  Uwe Schroder ,  Ulrich Mantz ,  Stefan Jakschik ,  Andreas Orth

IPC分类号： G01B11/22 ,  G01J3/453 ,  G01N21/21 ,  H01L21/337

CPC分类号： G01N21/211 ,  G01B11/22 ,  G01J3/453

摘要： The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer behavior of the semiconductor wafer which is brought about by the buried structure when the semiconductor wafer is irradiated with electromagnetic radiation in the infrared range and arises as a result of the significantly longer wavelengths of the radiation used in comparison with the lateral dimensions of the buried structure is utilized to determine the depth of the buried structure by spectrometric and/or ellipsometric methods.

摘要翻译： 本发明涉及一种用于确定半导体晶片中的掩埋结构的深度的方法。 根据本发明，当半导体晶片在红外范围内被电磁辐射照射时，由掩埋结构引起的半导体晶片的层行为，并且由于与所使用的辐射相比显着更长的辐射波长而产生 掩埋结构的横向尺寸用于通过光谱测量和/或椭偏方法确定掩埋结构的深度。

公开(公告)号：US20050164464A1

公开(公告)日：2005-07-28

申请号：US11042326

申请日：2005-01-26

申请人： Thomas Hecht ,  Matthias Goldbach ,  Uwe Schroder

发明人： Thomas Hecht ,  Matthias Goldbach ,  Uwe Schroder

IPC分类号： C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/314 ,  H01L21/334 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L21/20 ,  H01L21/76

CPC分类号： C23C16/045 ,  C23C16/45525 ,  H01L21/3065 ,  H01L21/3141 ,  H01L27/10808 ,  H01L27/10829 ,  H01L27/10852 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate surface. The covering layer is patterned in a direction which is vertical with respect to the substrate surface by limiting a process quantity of at least one precursor material and/or by temporarily limiting the deposition process, and is formed as a functional layer or mask for subsequent process steps.

摘要翻译： 在通常为半导体晶片的衬底（其形式为浮雕形式的衬底表面）上，使用沉积工艺来提供在相对于衬底表面垂直或倾斜的工艺表面上的覆盖层 。 通过限制至少一种前体材料的工艺量和/或通过临时限制沉积工艺，将覆盖层图案化成相对于衬底表面垂直的方向，并形成为后续工艺的功能层或掩模 脚步。

公开(公告)号：US20070111547A1

公开(公告)日：2007-05-17

申请号：US11582656

申请日：2006-10-18

申请人： Thomas Hecht ,  Stefan Jakschik ,  Christian Kapteyn

发明人： Thomas Hecht ,  Stefan Jakschik ,  Christian Kapteyn

IPC分类号： H01L21/31

CPC分类号： H01L21/31111 ,  H01L21/28202 ,  H01L21/823857 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/78

摘要： In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal oxide or a metal oxynitride. The nitrided layer is removed selectively with respect to the dielectric layer in a predetermined etching medium.

摘要翻译： 在制造半导体结构体的方法中，提供了基板，在基板上形成包含至少一种金属氧化物的电介质层，并且从电介质层形成氮化层。 氮化层包括至少一种对应于金属氧化物的金属氮化物或金属氮氧化物。 在预定的蚀刻介质中相对于电介质层选择性地去除氮化层。

公开(公告)号：US07176514B2

公开(公告)日：2007-02-13

申请号：US10413812

申请日：2003-04-15

申请人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

发明人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

IPC分类号： H01L27/108 ,  H01L21/76

CPC分类号： H01L21/02238 ,  C25D11/02 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L21/31687 ,  H01L27/1085

摘要： A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

摘要翻译： 用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流 衬底跟随材料在与缺陷相邻的衬底的部分中。 还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。