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    DMA Control Circuit with Quality of Service Indications
    1.
    发明公开
    DMA Control Circuit with Quality of Service Indications 审中-公开

    公开(公告)号：US20240143530A1

    公开(公告)日：2024-05-02

    申请号：US18404449

    申请日：2024-01-04

    Applicant: Apple Inc.

    Inventor： Brett D. George ,  Rohit K. Gupta ,  Do Kyung Kim ,  Paul W. Glendenning

    IPC: G06F13/28

    CPC classification number: G06F13/28 ,  G06F2213/28

    Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

    Application aware SoC memory cache partitioning
    6.
    发明授权
    Application aware SoC memory cache partitioning 有权

    公开(公告)号：US11232033B2

    公开(公告)日：2022-01-25

    申请号：US16530216

    申请日：2019-08-02

    Applicant: Apple Inc.

    Inventor： Wolfgang H. Klingauf ,  Connie W. Cheung ,  Rohit K. Gupta ,  Rohit Natarajan ,  Vanessa Cristina Heppolette ,  Varaprasad V. Lingutla ,  Muditha Kanchana

    IPC: G06F12/0842 ,  G06F12/0895

    Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.

    DMA control circuit with quality of service indications
    7.
    发明授权
    DMA control circuit with quality of service indications 有权

    公开(公告)号：US11886365B2

    公开(公告)日：2024-01-30

    申请号：US17475074

    申请日：2021-09-14

    Applicant: Apple Inc.

    Inventor： Brett D. George ,  Rohit K. Gupta ,  Do Kyung Kim ,  Paul W. Glendenning

    IPC: G06F13/28

    CPC classification number: G06F13/28 ,  G06F2213/28

    Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

    Communication channels with both shared and independent resources
    9.
    发明授权
    Communication channels with both shared and independent resources 有权

    公开(公告)号：US11824795B2

    公开(公告)日：2023-11-21

    申请号：US17455321

    申请日：2021-11-17

    Applicant: Apple Inc.

    Inventor： Rohit K. Gupta ,  Gregory S. Mathews ,  Harshavardhan Kaushikkar ,  Jeonghee Shin ,  Rohit Natarajan

    IPC: H04L12/801 ,  H04L47/80 ,  H04L47/25 ,  H04L47/10

    CPC classification number: H04L47/805 ,  H04L47/25 ,  H04L47/39

    Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

    System on a chip that drives display when CPUs are powered down
    10.
    发明授权
    System on a chip that drives display when CPUs are powered down 有权

    公开(公告)号：US11822416B2

    公开(公告)日：2023-11-21

    申请号：US17934976

    申请日：2022-09-23

    Applicant: Apple Inc.

    Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

    IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3228 ,  H04B17/318

    CPC classification number: G06F1/3287 ,  G06F1/3228 ,  H04B17/318

    Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

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