公开(公告)号：US11735467B2

公开(公告)日：2023-08-22

申请号：US17558848

申请日：2021-12-22

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  Sankuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar ,  Anchuan Wang

IPC: H01L21/764 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/41791

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

公开(公告)号：US20230064183A1

公开(公告)日：2023-03-02

申请号：US17897375

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

公开(公告)号：US20220068640A1

公开(公告)日：2022-03-03

申请号：US17004262

申请日：2020-08-27

Applicant: Applied Materials, Inc.

Inventor： Huiyuan Wang ,  Susmit Singha Roy ,  Takehito Koshizawa ,  Bo Qi ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: H01L21/02 ,  H01L29/16

Abstract: Examples of the present technology include semiconductor processing methods to form diffusion barriers for germanium in a semiconductor structure. The methods may include forming a semiconductor layer stack from pairs of Si-and-SiGe layers. The Si-and-SiGe layer pairs may be formed by forming a silicon layer, and then forming the germanium barrier layer of the silicon layer. In some embodiments, the germanium-barrier layer may be less than or about 20 Å. A silicon-germanium layer may be formed on the germanium-barrier layer to complete the formation of the Si-and-SiGe layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the SiGe layer may be characterized by greater than or about 5 atom % germanium. Examples of the present technology also include semiconductor structures that include a silicon-germanium layer, a germanium-barrier layer, and a silicon layer.

公开(公告)号：US10707061B2

公开(公告)日：2020-07-07

申请号：US15581425

申请日：2017-04-28

Applicant: Applied Materials, Inc.

Inventor： Soonam Park ,  Yufei Zhu ,  Edwin C. Suarez ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Jiayin Huang

IPC: H01J37/32 ,  H01L21/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  C23C16/455 ,  C23C16/50 ,  C23C16/505 ,  C23C16/52

Abstract: A method of conditioning internal surfaces of a plasma source includes flowing first source gases into a plasma generation cavity of the plasma source that is enclosed at least in part by the internal surfaces. Upon transmitting power into the plasma generation cavity, the first source gases ignite to form a first plasma, producing first plasma products, portions of which adhere to the internal surfaces. The method further includes flowing the first plasma products out of the plasma generation cavity toward a process chamber where a workpiece is processed by the first plasma products, flowing second source gases into the plasma generation cavity. Upon transmitting power into the plasma generation cavity, the second source gases ignite to form a second plasma, producing second plasma products that at least partially remove the portions of the first plasma products from the internal surfaces.

公开(公告)号：US20200058516A1

公开(公告)日：2020-02-20

申请号：US16665834

申请日：2019-10-28

Applicant: Applied Materials, Inc.

Inventor： Soonam Park ,  Yufei Zhu ,  Edwin C. Suarez ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Jiayin Huang

IPC: H01L21/3213 ,  H01J37/32 ,  C23C16/52 ,  C23C16/455 ,  C23C16/452 ,  C23C16/44 ,  H01L21/66 ,  H01L21/67 ,  H01L21/311 ,  H01L21/3065 ,  C23C16/50 ,  G01J3/02 ,  G01J3/443

Abstract: In an embodiment, a plasma source includes a first electrode, configured for transfer of one or more plasma source gases through first perforations therein; an insulator, disposed in contact with the first electrode about a periphery of the first electrode; and a second electrode, disposed with a periphery of the second electrode against the insulator such that the first and second electrodes and the insulator define a plasma generation cavity. The second electrode is configured for movement of plasma products from the plasma generation cavity therethrough toward a process chamber. A power supply provides electrical power across the first and second electrodes to ignite a plasma with the one or more plasma source gases in the plasma generation cavity to produce the plasma products. One of the first electrode, the second electrode and the insulator includes a port that provides an optical signal from the plasma.

公开(公告)号：US10468259B2

公开(公告)日：2019-11-05

申请号：US15966787

申请日：2018-04-30

Applicant: Applied Materials, Inc.

Inventor： Vinod Robert Purayath ,  Nitin K. Ingle

IPC: H01L27/115 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/06 ,  H01L27/1157

Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.

公开(公告)号：US10424485B2

公开(公告)日：2019-09-24

申请号：US15173824

申请日：2016-06-06

Applicant: Applied Materials, Inc.

Inventor： Nitin K. Ingle ,  Dmitry Lubomirsky ,  Xinglong Chen ,  Shankar Venkataraman

IPC: H01L21/3065 ,  H01J37/32

Abstract: Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate processing region. The oxygen-containing precursor may be flowed into the region while forming a plasma in the first remote plasma region to produce oxygen-containing plasma effluents. The methods may also include flowing a fluorine-containing precursor into a second remote plasma region fluidly coupled with the substrate processing region while forming a plasma in the second remote plasma region to produce fluorine-containing plasma effluents. The methods may include flowing the oxygen-containing plasma effluents and fluorine-containing plasma effluents into the processing region, and using the effluents to etch a patterned substrate housed in the substrate processing region.

公开(公告)号：US09947549B1

公开(公告)日：2018-04-17

申请号：US15332849

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Zhenjiang Cui ,  Soonam Park ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C23F3/00 ,  H01L21/3213 ,  H01L21/311 ,  C23F1/12 ,  H01J37/32 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/32136 ,  C23F1/12 ,  H01J37/32091 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/02071 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/32138 ,  H01L21/7684

Abstract: Methods are described herein for etching cobalt films which are difficult to volatize. The methods include exposing a cobalt film to a bromine or chlorine-containing precursor with a concurrent local plasma which applies a bias to the impinging etchants. Cobalt halide is formed on the surface at the same time an amorphized cobalt layer is formed near the surface. A carbon-and-nitrogen-containing precursor is later delivered to the substrate processing region to form volatile cobalt complexes which desorb from the surface of the cobalt film. Cobalt may be selectively removed. The concurrent production of cobalt halide and amorphized regions was found to markedly increase the overall etch rate and markedly improve surface smoothness upon exposure to the carbon-and-nitrogen-containing precursor. All the recited steps may now be performed in the same substrate processing chamber.

公开(公告)号：US20180102259A1

公开(公告)日：2018-04-12

申请号：US15332849

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Zhenjiang Cui ,  Soonam Park ,  Nitin K. Ingle

IPC: H01L21/3213 ,  H01L21/311 ,  C23F1/12 ,  H01J37/32

CPC classification number: H01L21/32136 ,  C23F1/12 ,  H01J37/32091 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/02071 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/32138 ,  H01L21/7684

Abstract: Methods are described herein for etching cobalt films which are difficult to volatize. The methods include exposing a cobalt film to a bromine or chlorine-containing precursor with a concurrent local plasma which applies a bias to the impinging etchants. Cobalt halide is formed on the surface at the same time an amorphized cobalt layer is formed near the surface. A carbon-and-nitrogen-containing precursor is later delivered to the substrate processing region to form volatile cobalt complexes which desorb from the surface of the cobalt film. Cobalt may be selectively removed. The concurrent production of cobalt halide and amorphized regions was found to markedly increase the overall etch rate and markedly improve surface smoothness upon exposure to the carbon-and-nitrogen-containing precursor. All the recited steps may now be performed in the same substrate processing chamber.

公开(公告)号：US20170148642A1

公开(公告)日：2017-05-25

申请号：US15337781

申请日：2016-10-28

Applicant: APPLIED MATERIALS, INC.

Inventor： Fei Wang ,  Mikhail Korolik ,  Nitin K. Ingle ,  Anchuan Wang ,  Robert Jan Visser

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31144 ,  C09D183/08 ,  H01J37/3244 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/31116

Abstract: Methods of etching silicon nitride faster than silicon or silicon oxide are described. Methods of selectively depositing additional material onto the silicon nitride are also described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent exposure to an etchant or a deposition precursor may then be used to selectively remove silicon nitride or to selectively deposit additional material on the silicon nitride.