公开(公告)号：US20160049348A1

公开(公告)日：2016-02-18

申请号：US14518947

申请日：2014-10-20

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Galen KIRKPATRICK ,  Edward LAW ,  Reza KHAN ,  Ming Wang SZE

IPC: H01L23/31 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3178 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/544 ,  H01L24/14 ,  H01L24/46 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface.

Abstract translation: 半导体封装包括包含有源电路层的半导体单元。 半导体封装还包括有源电路层上的多个接合焊盘，其被配置为连接到对应的外部导电连接器。 半导体封装还包括填充有源电路层的沟槽边缘的保护性密封剂涂层。 保护性密封剂涂层包含外部晶片单面。

公开(公告)号：US20150340308A1

公开(公告)日：2015-11-26

申请号：US14323759

申请日：2014-07-03

Applicant: Broadcom Corporation

Inventor： Edward LAW ,  Sam Ziqun Zhao ,  Kunzhong Hu ,  Rezaur Rahman Khan

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05672 ,  H01L2224/06135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00014

Abstract: A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

Abstract translation: 描述了重构的半导体封装和制造重构的半导体封装的方法。 芯片附着基板的阵列形成在载体上。 半导体器件安装在每个裸片附着衬底的第一表面上。 插入器基板安装在每个半导体器件上。 插入器基板电连接到各个管芯附着基板的第一表面。 将模塑料填充在安装到它们各自的管芯附着衬底上的插入器衬底之内和之间的开放空间中，以形成重构的半导体封装的阵列。 电连接被安装到管芯附接衬底的第二表面。 重新组装的半导体封装的阵列通过模具化合物在每个裸片附着衬底和相应的安装的插入器衬底之间分割。

公开(公告)号：US20150302974A1

公开(公告)日：2015-10-22

申请号：US14684256

申请日：2015-04-10

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun ZHAO ,  Edward LAW ,  Sampath Komarapalayam KARIKALAN ,  Neal Andrew KISTLER ,  Rezaur Rahman KHAN ,  Pieter VORENKAMP

IPC: H01F27/28 ,  H05K1/18 ,  H01F41/02 ,  H01F41/04 ,  H01F27/24 ,  H01F27/40

CPC classification number: H05K1/181 ,  H01F17/0013 ,  H01F17/045 ,  H01F38/14 ,  H01F41/046 ,  H01F2017/0053 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L2224/16225

Abstract: A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.

Abstract translation: 三维（3-D）磁芯装置包括基板，形成在基板上的第一磁性壳以及嵌入在形成于第一磁性壳上的第一绝缘体层中的第一组导电迹线。 磁芯平面形成在第一绝缘体层上，第二组导电迹线嵌入形成在磁芯平面上的第二绝缘体层中。 第二磁性壳体形成在第二绝缘体层上，并且第一和第二组导电迹线通过使用导电通孔导电耦合。