公开(公告)号：US20130295723A1

公开(公告)日：2013-11-07

申请号：US13929240

申请日：2013-06-27

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman KHAN ,  Sam Ziqun Zhao

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit (IC) package is provided. The method includes mounting a fast plurality of contact members on a surface of a package member, and coupling a second plurality of contact members located on a first surface of an interposer substrate to corresponding ones of the first plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the first plurality of contact members.

Abstract translation: 提供一种制造集成电路（IC）封装的方法。 该方法包括将快速多个接触构件安装在封装构件的表面上，以及将位于中介层基板的第一表面上的第二多个接触构件与第一多个接触构件中的相应接触构件连接。 插入器基板被配置为使得安装到插入器基板的第二表面的电路构件电耦合到第一多个接触构件。

公开(公告)号：US20160148890A1

公开(公告)日：2016-05-26

申请号：US15012879

申请日：2016-02-02

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman KHAN ,  Sam Ziqun ZHAO

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/50 ,  H01L23/42

CPC classification number: H01L24/16 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/42 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2021/60262 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located at a corresponding hotspot on a surface of th28e IC die. The package also includes a thermally conductive interposer which is thermally coupled to the IC die at the contact pads. In another aspect, an underfill material fills a space between the IC die and the interposer. The interposer may also be electrically coupled to the IC die. In an aspect, the interposer and the IC die are coupled through thermal interconnects or “nodules.”

Abstract translation: 描述了用于改进IC器件封装的方法，系统和装置。 在一方面，（IC）器件封装包括具有在一个或多个接触焊盘处的IC管芯，每个接触焊盘位于th28e IC管芯的表面上的相应热点处。 封装还包括热接触插入件，其在接触焊盘处热耦合到IC管芯。 在另一方面，底部填充材料填充IC管芯和插入件之间的空间。 插入器也可以电耦合到IC管芯。 在一方面，插入器和IC管芯通过热互连或“结节”耦合。

公开(公告)号：US20170117251A1

公开(公告)日：2017-04-27

申请号：US14954679

申请日：2015-11-30

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman KHAN ,  Sam Ziqun ZHAO

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L23/50 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0905 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06589

Abstract: A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.

公开(公告)号：US20150302974A1

公开(公告)日：2015-10-22

申请号：US14684256

申请日：2015-04-10

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun ZHAO ,  Edward LAW ,  Sampath Komarapalayam KARIKALAN ,  Neal Andrew KISTLER ,  Rezaur Rahman KHAN ,  Pieter VORENKAMP

IPC: H01F27/28 ,  H05K1/18 ,  H01F41/02 ,  H01F41/04 ,  H01F27/24 ,  H01F27/40

CPC classification number: H05K1/181 ,  H01F17/0013 ,  H01F17/045 ,  H01F38/14 ,  H01F41/046 ,  H01F2017/0053 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L2224/16225

Abstract: A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.

Abstract translation: 三维（3-D）磁芯装置包括基板，形成在基板上的第一磁性壳以及嵌入在形成于第一磁性壳上的第一绝缘体层中的第一组导电迹线。 磁芯平面形成在第一绝缘体层上，第二组导电迹线嵌入形成在磁芯平面上的第二绝缘体层中。 第二磁性壳体形成在第二绝缘体层上，并且第一和第二组导电迹线通过使用导电通孔导电耦合。

公开(公告)号：US20150069637A1

公开(公告)日：2015-03-12

申请号：US14031000

申请日：2013-09-18

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Rezaur Rahman KHAN

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/30131 ,  H01L2224/30141 ,  H01L2224/30179 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

Abstract translation: 集成电路（IC）封装包括具有第一表面和与第一表面相对的第二表面的IC管芯。 IC封装包括耦合到IC管芯的第二表面的第一接触构件。 IC封装包括具有第一表面和与第一表面相对的第二表面的底部衬底，其中底部衬底的第一表面经由第一接触构件联接到IC管芯的第二表面。 IC封装包括通过粘合剂材料耦合到IC管芯的第一表面的插入器基板，其中粘合材料设置在中介层基板的至少一个表面上。 IC封装包括沿着插入器衬底的周边耦合的第二接触构件，其中插入器衬底经由第二接触构件联接到底部衬底的第一表面。

公开(公告)号：US20160155728A1

公开(公告)日：2016-06-02

申请号：US15018818

申请日：2016-02-08

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Rezaur Rahman KHAN ,  Pieter VORENKAMP ,  Sampath K.V. KARIKALAN ,  Kevin Kunzhong HU ,  Xiangdong CHEN

IPC: H01L25/10 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/50 ,  H01L21/78 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the, top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

Abstract translation: 本公开的示例性实施方案包括具有来自位于底部重构晶片的底模上方的顶部重构晶片的顶模的堆叠封装。 顶部模具和底部模具通过绝缘装置彼此绝缘。 顶模和底模也通过绝缘装置互连。 绝缘装置可以包括在顶模侧面的顶部模塑料和位于底模侧面的底部模塑料。 顶模和底模可以通过至少顶部模塑料相互连接。 此外，顶模和底模可以通过在绝缘装置内延伸的导电通孔相互连接。

公开(公告)号：US20150249061A1

公开(公告)日：2015-09-03

申请号：US14715484

申请日：2015-05-18

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Rezaur Rahman KHAN

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/30131 ,  H01L2224/30141 ,  H01L2224/30179 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

公开(公告)号：US20150235992A1

公开(公告)日：2015-08-20

申请号：US14701388

申请日：2015-04-30

Applicant: BROADCOM CORPORATION

Inventor： Sampath K. KARIKALAN ,  Sam Ziqun ZHAO ,  Kevin Kunzhong HU ,  Rezaur Rahman KHAN ,  Pieter VORENKAMP ,  Xiangdong CHEN

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/538 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/152 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

Abstract translation: 这里公开了包括桥插入器的半导体封装的各种实施方式。 一个示例性实现包括具有位于桥插入件上方的第一部分的第一有源管芯和不位于桥插入件上的第二部分。 半导体封装还包括具有位于桥插入件上方的第一部分的第二有源管芯和不位于桥插入件上的第二部分。 第一有源裸片的第二部分和第二有源裸片的第二部分包括安装在封装衬底上的焊球，并且被配置为使用焊球将电信号传送到封装衬底，并且不使用贯穿半导体通孔（TSV ）。

公开(公告)号：US20150200149A1

公开(公告)日：2015-07-16

申请号：US14668276

申请日：2015-03-25

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Rezaur Rahman KHAN

IPC: H01L23/367 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00 ,  H01L23/433 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L21/565 ,  H01L22/10 ,  H01L23/315 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81897 ,  H01L2224/83101 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.

Abstract translation: 本文描述了用于改进的集成电路（IC）封装的方法和装置。 一方面，IC器件封装包括具有接触焊盘的IC管芯，其中接触焊盘位于IC管芯的热点上。 热点热耦合到热互连构件。 在一方面，包装被包封在模具化合物中。 在另一方面，散热器附接到模具化合物，并且热耦合到热互连构件。 另一方面，热互连构件热耦合在散热器和衬底之间。