公开(公告)号：US20130234326A1

公开(公告)日：2013-09-12

申请号：US13604481

申请日：2012-09-05

Applicant: Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

Inventor： Chul KIM ,  Jae Jin LEE ,  Jong Chern LEE

IPC: H01L23/00 ,  H01L21/82

CPC classification number: H01L23/562 ,  H01L21/82 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip.

Abstract translation: 半导体装置包括具有贯通硅通孔（TSV）的第一半导体芯片和也具有TSV的第二半导体芯片，其中各个半导体芯片垂直堆叠并通过导电连接构件连接，而无需附加凸块 在导电连接部件和第二半导体芯片之间。

公开(公告)号：US20130241054A1

公开(公告)日：2013-09-19

申请号：US13604449

申请日：2012-09-05

Applicant: Chul KIM ,  Jong Chern LEE

Inventor： Chul KIM ,  Jong Chern LEE

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16013 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

Abstract translation: 在半导体装置中，包括贯通硅通孔的多个半导体芯片在垂直方向堆叠，其中形成在每个半导体芯片中的贯通硅通孔突出超过每个半导体芯片的高度。

公开(公告)号：US20120153280A1

公开(公告)日：2012-06-21

申请号：US13041003

申请日：2011-03-04

Applicant: Dae-Suk KIM ,  Jong-Chern LEE ,  Chul KIM

Inventor： Dae-Suk KIM ,  Jong-Chern LEE ,  Chul KIM

IPC: H01L23/52

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  H01L23/481 ,  H01L24/05 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

Abstract translation: 在晶圆级别检测贯通硅通孔是否具有缺陷的集成电路。 集成电路包括：半导体衬底;通孔构造成形成在半导体衬底中以从半导体衬底的表面延伸到一定深度的通硅通孔，输出焊盘和电流通路提供单元，其被配置为提供电流， 在测试模式期间，在半导体衬底和贯穿硅通孔之间流动到输出焊盘。

公开(公告)号：US20160049511A1

公开(公告)日：2016-02-18

申请号：US14826439

申请日：2015-08-14

Applicant: Jin-Bum KIM ,  Seok-Hoon KIM ,  Chul KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Bon-Young KOO

Inventor： Jin-Bum KIM ,  Seok-Hoon KIM ,  Chul KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Bon-Young KOO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/32

CPC classification number: H01L29/7848 ,  H01L21/3221 ,  H01L29/165 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785

Abstract: Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

Abstract translation: 提供了在衬底上包括有源图案的半导体器件，在有源图案上的第一和第二栅电极，并且相对于彼此在第一方向上布置，并且第一沟槽中的第一源/漏区延伸到有源图案之间 第一和第二栅电极。 第一源极/漏极区域包括第一外延层，其被配置为填充第一沟槽并且包括起始于第一外延层的顶部并延伸朝向第一外延层的底部的至少一个平面缺陷。

公开(公告)号：US20110241653A1

公开(公告)日：2011-10-06

申请号：US12970921

申请日：2010-12-16

Applicant: Chul KIM

Inventor： Chul KIM

IPC: G01R25/00

CPC classification number: H03K19/0005

Abstract: An impedance calibration apparatus of a semiconductor integrated circuit includes: a D/A conversion unit configured to receive a code and generate an analog voltage depending on the code; a virtual code voltage generation unit configured to detect a level of the analog voltage and generate a plurality of virtual code voltages based on the level of the analog voltage; a comparison unit configured to receive the plurality of virtual code voltages and a reference voltage as inputs, and compare the plurality of virtual code voltages with the reference voltage to generate a plurality of comparison signals; and a code generation unit configured to receive the plurality of comparison signals and generate the code using the plurality of comparison signals.

Abstract translation: 半导体集成电路的阻抗校准装置包括：D / A转换单元，被配置为接收代码并根据代码生成模拟电压; 虚拟代码电压生成单元，被配置为基于模拟电压的电平来检测模拟电压的电平并生成多个虚拟代码电压; 比较单元，被配置为接收所述多个虚拟代码电压和参考电压作为输入，并且将所述多个虚拟代码电压与所述参考电压进行比较以生成多个比较信号; 以及代码生成单元，被配置为接收所述多个比较信号，并使用所述多个比较信号生成所述代码。

公开(公告)号：US20130038569A1

公开(公告)日：2013-02-14

申请号：US13312144

申请日：2011-12-06

Applicant: Chul KIM ,  Su-Bin PARK ,  Seung Hwan MOON ,  Byoung Jun LEE

Inventor： Chul KIM ,  Su-Bin PARK ,  Seung Hwan MOON ,  Byoung Jun LEE

IPC: G06F3/044 ,  G06F3/045

CPC classification number: G06F3/044 ,  G06F3/0412 ,  G06F2203/04103

Abstract: A display device includes: a first insulation substrate having an upper surface and a lower surface; a transparent conductive layer disposed on the upper surface of the first insulation substrate; a gate line disposed on the lower surface of the first insulation substrate; a gate insulating layer disposed on the gate line; a semiconductor layer disposed on the gate insulating layer; a data line disposed on the semiconductor layer and connected to a source electrode and a drain electrode facing the source electrode; and a pixel electrode electrically connected to the drain electrode, where the gate line, the gate insulating layer, the semiconductor layer and the data line are sequentially disposed on the lower surface of the first insulation substrate.

Abstract translation: 显示装置包括：具有上表面和下表面的第一绝缘基板; 设置在所述第一绝缘基板的上表面上的透明导电层; 设置在所述第一绝缘基板的下表面上的栅极线; 设置在栅极线上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体层; 数据线，设置在所述半导体层上，并连接到面对所述源电极的源电极和漏电极; 以及与所述漏电极电连接的像素电极，其中所述栅极线，所述栅极绝缘层，所述半导体层和所述数据线依次配置在所述第一绝缘基板的下表面上。

公开(公告)号：US20130265244A1

公开(公告)日：2013-10-10

申请号：US13571459

申请日：2012-08-10

Applicant: Chul KIM ,  Su Bin PARK ,  Ji Woong KIM ,  Seung Hwan MOON ,  Nam-Hee GOO ,  Seok-Hyun JUNG

Inventor： Chul KIM ,  Su Bin PARK ,  Ji Woong KIM ,  Seung Hwan MOON ,  Nam-Hee GOO ,  Seok-Hyun JUNG

IPC: G06F3/041

CPC classification number: G06F3/0412 ,  G06F3/044

Abstract: A display device includes a first substrate including a first surface, on which a touch by an external object occurs, and a second surface opposite to the first surface, a plurality of driving signal lines positioned on the second surface of the first substrate, where the plurality of driving signal lines transmits a driving signal for displaying an image, a plurality of pixels including a plurality of switching elements connected to the plurality of driving signal lines, a sensing signal line positioned on one of the first surface and the second surface of the first substrate, where the sensing signal line transmits a sensing signal generated based on the touch by the external object, and a touch sensor unit including a sensing capacitor defined by at least one driving signal line of the plurality of driving signal lines and the sensing signal line.

Abstract translation: 显示装置包括：第一基板，包括第一表面，外部物体发生触摸，第一表面与第一表面相对的第二表面;位于第一基板的第二表面上的多个驱动信号线， 多个驱动信号线传输用于显示图像的驱动信号，多个像素包括连接到多个驱动信号线的多个开关元件，位于第一表面和第二表面中的一个上的感测信号线 第一基板，其中感测信号线传输基于外部物体的触摸产生的感测信号，以及触摸传感器单元，其包括由多个驱动信号线中的至少一个驱动信号线和感测信号限定的感测电容器 线。

公开(公告)号：US20130088444A1

公开(公告)日：2013-04-11

申请号：US13608167

申请日：2012-09-10

Applicant: Chul KIM ,  Ji-Woong KIM ,  Su-Bin PARK ,  Seung-Hwan MOON ,  Byoung-Jun LEE

Inventor： Chul KIM ,  Ji-Woong KIM ,  Su-Bin PARK ,  Seung-Hwan MOON ,  Byoung-Jun LEE

IPC: G06F3/041

CPC classification number: G06F3/0416 ,  G02F1/13338 ,  G06F3/044

Abstract: A method of driving a touch display panel includes sequentially providing gate signals to a plurality of gate lines, outputting data signals to a plurality of data lines, the data lines being disposed on the first surface and crossing the gate lines, and reading out a first sensing signal through a plurality of sensing lines in response to the gate signals. The gate lines are disposed on a first surface of a base substrate, the touch display panel including the base substrate. The data signals are synchronized with the gate signals. The sensing line is disposed on a second surface of the base substrate, the second surface being opposite to the first surface.

Abstract translation: 驱动触摸显示面板的方法包括向多条栅极线顺序地提供栅极信号，将数据信号输出到多条数据线，数据线被布置在第一表面上并与栅极线交叉，并且读出第一 响应于门信号通过多个感测线感测信号。 栅极线设置在基底基板的第一表面上，触摸显示面板包括基底。 数据信号与门信号同步。 感测线设置在基底基板的第二表面上，第二表面与第一表面相对。

公开(公告)号：US20130169587A1

公开(公告)日：2013-07-04

申请号：US13477247

申请日：2012-05-22

Applicant: Chul KIM ,  Ji Woong KIM ,  Su Bin PARK ,  Byoung Jun LEE ,  Seung Hwan MOON

Inventor： Chul KIM ,  Ji Woong KIM ,  Su Bin PARK ,  Byoung Jun LEE ,  Seung Hwan MOON

IPC: G06F3/044 ,  G09G3/30

CPC classification number: G06F3/044 ,  G06F3/0412

Abstract: A display device includes: a first display panel; a second display panel opposite to the first display panel; and an electro-optical active layer between the first display panel and the second display panel, wherein the first display panel includes a thin film transistor including a gate electrode, a source electrode, a drain electrode and a semiconductor layer, a gate line configured to transmit a gate signal to the gate electrode of the transistor and extending in a first direction, and a sensing electrode extending in the first direction and overlapping the gate line, where the sensing electrode and the gate electrode define a capacitor.

Abstract translation: 显示装置包括：第一显示面板; 与第一显示面板相对的第二显示面板; 以及在所述第一显示面板和所述第二显示面板之间的电光活性层，其中所述第一显示面板包括薄膜晶体管，所述薄膜晶体管包括栅电极，源电极，漏电极和半导体层，栅线配置为 将栅极信号发送到晶体管的栅电极并沿第一方向延伸，以及感测电极，其沿第一方向延伸并与栅极线重叠，其中感测电极和栅电极限定电容器。

公开(公告)号：US20130162313A1

公开(公告)日：2013-06-27

申请号：US13604042

申请日：2012-09-05

Applicant: Chul KIM

Inventor： Chul KIM

IPC: H03L7/06

CPC classification number: G11C7/04 ,  G11C7/109

Abstract: A semiconductor apparatus includes a first structural body including a first temperature voltage generation unit configured to generate first and second temperature voltages which have different voltage level variations according to a temperature variation, in response to a temperature measurement command, and a first temperature information determination unit configured to generate first temperature information depending on a difference between levels of the first and second temperature voltages; and a second structural body including a second temperature voltage generation unit configured to generate a third temperature voltage and a fourth temperature voltage which have different voltage level variations according to a temperature variation, when a predetermined time elapses after the first and second temperature voltages are generated from the first structural body, and a second temperature information determination unit configured to generate second temperature information depending on a difference between levels of the third and fourth temperature voltages.

Abstract translation: 一种半导体装置，包括：第一结构体，包括第一温度电压生成单元，其被配置为响应于温度测量命令，根据温度变化产生具有不同的电压电平变化的第一和第二温度电压;以及第一温度信息确定单元 被配置为根据第一和第二温度电压的电平之差产生第一温度信息; 以及第二结构体，包括第二温度电压产生单元，被配置为当在产生第一和第二温度电压之后经过预定时间时，根据温度变化产生具有不同电压电平变化的第三温度电压和第四温度电压 以及第二温度信息确定单元，被配置为根据第三和第四温度电压的电平之间的差产生第二温度信息。