公开(公告)号：US08030668B2

公开(公告)日：2011-10-04

申请号：US11935904

申请日：2007-11-06

申请人： Digh Hisamoto ,  Shinichi Saito ,  Shinichiro Kimura

发明人： Digh Hisamoto ,  Shinichi Saito ,  Shinichiro Kimura

IPC分类号： H01L27/15

CPC分类号： H01L27/15 ,  G02B6/13 ,  G02B6/43 ,  H01L33/02 ,  H01L33/34

摘要： A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.

摘要翻译： 提供了高发光效率的发光二极管，并且包括通过现有技术的硅工艺在硅衬底上形成的等价于其的硅或锗等IV族半导体作为基底部件，以及其波导管的制造方法。 本发明的发光二极管包括用于注入电子的第一电极，用于注入孔的第二电极和与第一和第二电极电连接的发光部分，其中发光部分由单晶硅制成， 具有面向第一表面的第一表面和第二表面，其中相对于第一表面和第二表面的平面取向（100），使与第一表面和第二表面成直角交叉的发光部分变薄，并且其中 具有高折射率的材料设置在薄膜部分周围。

公开(公告)号：US20080197362A1

公开(公告)日：2008-08-21

申请号：US11935904

申请日：2007-11-06

申请人： Digh HISAMOTO ,  Shinichi Saito ,  Shinichiro Kimura

发明人： Digh HISAMOTO ,  Shinichi Saito ,  Shinichiro Kimura

IPC分类号： H01L33/00

CPC分类号： H01L27/15 ,  G02B6/13 ,  G02B6/43 ,  H01L33/02 ,  H01L33/34

摘要： A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.

摘要翻译： 提供了高发光效率的发光二极管，并且包括通过现有技术的硅工艺在硅衬底上形成的等价于其的硅或锗等IV族半导体作为基底部件，以及其波导管的制造方法。 本发明的发光二极管包括用于注入电子的第一电极，用于注入孔的第二电极和与第一和第二电极电连接的发光部分，其中发光部分由单晶硅制成， 具有面对第一表面的第一表面和第二表面，其中相对于第一表面和第二表面的平面取向（100），使与第一表面和第二表面成直角交叉的发光部分变薄，并且其中 具有高折射率的材料设置在薄膜部分周围。

公开(公告)号：US08436333B2

公开(公告)日：2013-05-07

申请号：US11790283

申请日：2007-04-24

申请人： Shinichi Saito ,  Digh Hisamoto ,  Tadashi Arai ,  Takahiro Onai

发明人： Shinichi Saito ,  Digh Hisamoto ,  Tadashi Arai ,  Takahiro Onai

IPC分类号： H01L29/06

CPC分类号： H01L33/34 ,  H01S5/3224

摘要： A light-emitting device according to the present invention includes a first electrode unit for injecting an electron, a second electrode unit for injecting a hole, and light-emitting units and electrically connected to the first electrode unit and the second electrode unit respectively, wherein the light-emitting units and are formed of single-crystal silicon, the light-emitting units and having a first surface (topside surface) and a second surface (underside surface) opposed to the first surface, plane orientation of the first and second surfaces being set to a (100) plane, thicknesses of the light-emitting units and in a direction orthogonal to the first and second surfaces being made extremely thin.

摘要翻译： 根据本发明的发光器件包括用于注入电子的第一电极单元，用于注入孔的第二电极单元和发光单元，并分别与第一电极单元和第二电极单元电连接，其中 所述发光单元由单晶硅形成，所述发光单元具有与所述第一表面相对的第一表面（顶侧表面）和第二表面（下表面），所述第一表面和所述第二表面 设置为（100）面时，发光单元的厚度和与第一表面和第二表面正交的方向的厚度非常薄。

公开(公告)号：US07890898B2

公开(公告)日：2011-02-15

申请号：US12024107

申请日：2008-01-31

申请人： Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

发明人： Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.

摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。

公开(公告)号：US20130341729A1

公开(公告)日：2013-12-26

申请号：US13812181

申请日：2011-06-20

申请人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

发明人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

IPC分类号： H01L27/06

CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C16/0408 ,  H01L21/8249 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/1025 ,  H01L27/1026 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1004 ,  H01L29/1033 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7311 ,  H01L29/788 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.

摘要翻译： 提供了与MOSFET相比具有与常规MOSFET相同的可集成性的半导体元件，即在室温下S值小于60mV /阶的优异的开关特性。 组合MOSFET和具有隧道结的隧道双极晶体管配置了一个半导体元件，其相对于栅极电压的变化（S值小于60mV /次）显示出漏极电流的突然变化，即使在 低电压。

公开(公告)号：US09209171B2

公开(公告)日：2015-12-08

申请号：US13812181

申请日：2011-06-20

申请人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

发明人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/07 ,  H01L27/092 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H01L27/102 ,  G11C11/412

CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C16/0408 ,  H01L21/8249 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/1025 ,  H01L27/1026 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1004 ,  H01L29/1033 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7311 ,  H01L29/788 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.

摘要翻译： 提供了与MOSFET相比具有与常规MOSFET相同的可集成性的半导体元件，即在室温下S值小于60mV /阶的优异的开关特性。 组合MOSFET和具有隧道结的隧道双极晶体管配置了一个半导体元件，其相对于栅极电压的变化（S值小于60mV /次）显示出漏极电流的突然变化，即使在 低电压。

公开(公告)号：US07812398B2

公开(公告)日：2010-10-12

申请号：US12400324

申请日：2009-03-09

申请人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。

公开(公告)号：US20090132974A1

公开(公告)日：2009-05-21

申请号：US12024107

申请日：2008-01-31

申请人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

发明人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.

摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。

公开(公告)号：US20120287959A1

公开(公告)日：2012-11-15

申请号：US13521533

申请日：2011-01-28

申请人： Kazuki Tani ,  Shinichi Saito ,  Toshiki Sugawara ,  Youngkun Lee ,  Digh Hisamoto ,  Makoto Miura ,  Katsuya Oda

发明人： Kazuki Tani ,  Shinichi Saito ,  Toshiki Sugawara ,  Youngkun Lee ,  Digh Hisamoto ,  Makoto Miura ,  Katsuya Oda

IPC分类号： H01S5/22

CPC分类号： H01S5/3223 ,  H01L33/34 ,  H01L33/62 ,  H01L2924/0002 ,  H01S5/0207 ,  H01S5/021 ,  H01S5/0424 ,  H01S5/0425 ,  H01S5/1231 ,  H01S5/4031 ,  H01L2924/00

摘要： A germanium light-emitting device emitting light at high efficiency is provided by using germanium of small threading dislocation density. A germanium laser diode having a high quality germanium light-emitting layer is attained by using germanium formed over silicon dioxide. A germanium laser diode having a carrier density higher than the carrier density limit that can be injected by existent n-type germanium can be provided using silicon as an n-type electrode.

摘要翻译： 通过使用小螺纹位错密度的锗来提供高效率发光的锗发光器件。 通过使用在二氧化硅上形成的锗来获得具有高质量锗发光层的锗激光二极管。 可以使用硅作为n型电极来提供具有高于可由现有的n型锗注入的载流子密度极限的载流子密度的锗激光二极管。

公开(公告)号：US07531853B2

公开(公告)日：2009-05-12

申请号：US11746230

申请日：2007-05-09

申请人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L29/80 ,  H01L31/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。