公开(公告)号：US09136396B2

公开(公告)日：2015-09-15

申请号：US13905213

申请日：2013-05-30

申请人： Electronics and Telecommunications Research Institute

发明人： Sang Choon Ko ,  Jae Kyoung Mun ,  Byoung-Gue Min ,  Young Rak Park ,  Hokyun Ahn ,  Jeong-Jin Kim ,  Eun Soo Nam

IPC分类号： H01L29/66 ,  H01L29/808 ,  H01L29/417 ,  H01L29/778 ,  H01L29/43 ,  H01L29/45 ,  H01L29/20

CPC分类号： H01L29/808 ,  H01L21/76898 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7786

摘要： A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

摘要翻译： 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。

公开(公告)号：US08952422B2

公开(公告)日：2015-02-10

申请号：US13912350

申请日：2013-06-07

申请人： Electronics and Telecommunications Research Institute

发明人： Hokyun Ahn ,  Jong-Won Lim ,  Jeong-Jin Kim ,  Hae Cheon Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

摘要： A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

摘要翻译： 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。

公开(公告)号：US20140166615A1

公开(公告)日：2014-06-19

申请号：US13939530

申请日：2013-07-11

申请人： Electronics and Telecommunications Research Institute

发明人： Zin Sig KIM ,  Hokyun Ahn

IPC分类号： B29C59/02

CPC分类号： G03F7/0002

摘要： Mold structures for imprint lithography are provided. Mold chip patterns including patterns for nano structures are disposed on a mold substrate. A trench region is provided between the mold chip patterns. Protrusion portions protrude from a bottom surface of the trench region. The protrusion portions extend along the trench region in a plan view.

摘要翻译： 提供压印光刻的模具结构。 包括纳米结构的图案的模具芯片图案设置在模具基板上。 沟槽区域设置在模具芯片图案之间。 突出部分从沟槽区域的底表面突出。 突出部分在平面图中沿沟槽区域延伸。

公开(公告)号：US09634112B2

公开(公告)日：2017-04-25

申请号：US14633984

申请日：2015-02-27

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Seong-Il Kim ,  Sang Heung Lee ,  Dong Min Kang ,  Chull Won Ju ,  Jae Kyoung Mun

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/20 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/201 ,  H01L29/205 ,  H01L21/285

CPC分类号： H01L29/66462 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/28593 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/778 ,  H01L29/7786

摘要： A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

公开(公告)号：US09490214B2

公开(公告)日：2016-11-08

申请号：US14845435

申请日：2015-09-04

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC分类号： H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

公开(公告)号：US09159612B2

公开(公告)日：2015-10-13

申请号：US14021269

申请日：2013-09-09

申请人： Electronics and Telecommunications Research Institute

发明人： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC分类号： H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

摘要翻译： 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。

公开(公告)号：US20140167070A1

公开(公告)日：2014-06-19

申请号：US13938324

申请日：2013-07-10

申请人： Electronics and Telecommunications Research Institute

发明人： Young Rak PARK ,  Sang Choon Ko ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Sung-Bum Bae ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L29/16 ,  H01L29/66

CPC分类号： H01L29/66477 ,  H01L23/5225 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

摘要翻译： 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。

公开(公告)号：US20140159049A1

公开(公告)日：2014-06-12

申请号：US13905213

申请日：2013-05-30

申请人： Electronics and Telecommunications Research Institute

发明人： Sang Choon KO ,  Jae Kyoung Mun ,  Byoung-Gue Min ,  Young Rak Park ,  Hokyun Ahn ,  Jeong-Jin Kim ,  Eun Soo Nam

IPC分类号： H01L29/66 ,  H01L29/808

CPC分类号： H01L29/808 ,  H01L21/76898 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7786

摘要： A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

摘要翻译： 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。

公开(公告)号：US20140159050A1

公开(公告)日：2014-06-12

申请号：US13935096

申请日：2013-07-03

申请人： Electronics and Telecommunications Research Institute

发明人： Hyung Sup YOON ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Seong-ll Kim ,  Sang-Heung Lee ,  Dong Min Kang ,  Chull Won Ju ,  Jae Kyoung Mun

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/66462 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/28593 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/778 ,  H01L29/7786

摘要： A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

摘要翻译： 提供场效应晶体管。 场效应晶体管可以包括衬底上的覆盖层，覆盖层上的源欧姆电极和漏极欧姆电极，堆叠在覆盖层上以覆盖源极和漏极欧姆电极的第一绝缘层和第二绝缘层， 包括脚部和头部的栅格电极，所述脚部分连接到所述源欧姆电极和所述漏极欧姆电极之间的衬底，并且所述头部从所述腿部延伸以覆盖所述源极欧姆电极和所述漏极欧姆电极的顶表面 所述第二绝缘层，在所述第二绝缘层上覆盖所述栅格电极的第一平坦化层和所述第一平坦化层上的第一电极，所述第一电极连接到所述源欧姆电极或所述漏极欧姆电极。

公开(公告)号：US11916140B2

公开(公告)日：2024-02-27

申请号：US17508933

申请日：2021-10-22

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Sungjae Chang ,  Hokyun Ahn ,  Hyunwook Jung

IPC分类号： H01L29/778 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/7827 ,  H01L29/785

摘要： Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate.