公开(公告)号：US09825622B2

公开(公告)日：2017-11-21

申请号：US15217271

申请日：2016-07-22

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Woojin Chang ,  Sang Choon Ko ,  Jae Kyoung Mun ,  Young Rak Park

IPC分类号： H03K17/687 ,  H03K17/081 ,  H03K17/74

CPC分类号： H03K17/08104 ,  H03K17/0822 ,  H03K17/74

摘要： A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.

公开(公告)号：US09362744B2

公开(公告)日：2016-06-07

申请号：US14040102

申请日：2013-09-27

申请人： Electronics and Telecommunications Research Institute

发明人： Yong il Jun ,  Sang Choon Ko ,  Jae Kyoung Mun ,  Dae Woo Lee ,  Kyu-Seok Lee ,  Ho Young Kim ,  Chul Won Ju

IPC分类号： H02J3/00 ,  H02J1/04 ,  H02H3/20 ,  H02H7/10 ,  H02M1/00

CPC分类号： H02J1/04 ,  H02H3/20 ,  H02H7/10 ,  H02M2001/0074 ,  H02M2001/0087 ,  Y10T307/406

摘要： The inventive concept relates to a system supplying a constant current direct current power to serial loads connected in series with one another.The inventive concept is constituted by a constant current source power supply unit outputting a predetermined direct current, a load connection unit having the same rated current characteristic as the constant current source, a load connection unit having a rated current characteristic smaller than the constant current source, a load connection unit having a rated current characteristic greater than the constant current source, a load connection unit having a rated current characteristic greater or smaller than the constant current source and a circuit controlling or protecting them.

摘要翻译： 本发明的概念涉及向彼此串联连接的串联负载提供恒定电流直流电力的系统。 本发明的概念由输出预定直流电流的恒流源电源单元，与恒流源具有相同额定电流特性的负载连接单元构成，具有小于恒定电流源的额定电流特性的负载连接单元 具有大于恒流源的额定电流特性的负载连接单元，具有大于或小于恒流源的额定电流特性的负载连接单元和控制或保护恒流源的电路。

公开(公告)号：US09136396B2

公开(公告)日：2015-09-15

申请号：US13905213

申请日：2013-05-30

申请人： Electronics and Telecommunications Research Institute

发明人： Sang Choon Ko ,  Jae Kyoung Mun ,  Byoung-Gue Min ,  Young Rak Park ,  Hokyun Ahn ,  Jeong-Jin Kim ,  Eun Soo Nam

IPC分类号： H01L29/66 ,  H01L29/808 ,  H01L29/417 ,  H01L29/778 ,  H01L29/43 ,  H01L29/45 ,  H01L29/20

CPC分类号： H01L29/808 ,  H01L21/76898 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7786

摘要： A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

摘要翻译： 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。

公开(公告)号：US09490214B2

公开(公告)日：2016-11-08

申请号：US14845435

申请日：2015-09-04

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC分类号： H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

公开(公告)号：US09159612B2

公开(公告)日：2015-10-13

申请号：US14021269

申请日：2013-09-09

申请人： Electronics and Telecommunications Research Institute

发明人： Byoung-Gue Min ,  Sang Choon Ko ,  Jong-Won Lim ,  Hokyun Ahn ,  Hyung Sup Yoon ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/48 ,  H01L21/28

CPC分类号： H01L23/535 ,  H01L21/02365 ,  H01L21/28 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

摘要翻译： 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。

公开(公告)号：US20140167070A1

公开(公告)日：2014-06-19

申请号：US13938324

申请日：2013-07-10

申请人： Electronics and Telecommunications Research Institute

发明人： Young Rak PARK ,  Sang Choon Ko ,  Byoung-Gue Min ,  Jong-Won Lim ,  Hokyun Ahn ,  Sung-Bum Bae ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L29/16 ,  H01L29/66

CPC分类号： H01L29/66477 ,  H01L23/5225 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

摘要翻译： 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。

公开(公告)号：US10020201B2

公开(公告)日：2018-07-10

申请号：US15093814

申请日：2016-04-08

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Chi Hoon Jun ,  Sang Choon Ko ,  Seok-Hwan Moon ,  Woojin Chang ,  Sung-Bum Bae ,  Young Rak Park ,  Je Ho Na ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L23/367 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3205 ,  H01L23/473 ,  H01L23/467

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

公开(公告)号：US09755027B2

公开(公告)日：2017-09-05

申请号：US15265647

申请日：2016-09-14

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Hyung Seok Lee ,  Ki Hwan Kim ,  Sang Choon Ko ,  Zin-Sig Kim ,  Jeho Na ,  Eun Soo Nam ,  Young Rak Park ,  Junbo Park ,  Chi hoon Jun ,  Dong Yun Jung

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/417

CPC分类号： H01L29/402 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

摘要： Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.

公开(公告)号：US09159583B2

公开(公告)日：2015-10-13

申请号：US14310784

申请日：2014-06-20

申请人： Electronics and Telecommunications Research Institute

发明人： Sang Choon Ko ,  Jae Kyoung Mun ,  Woojin Chang ,  Sung-Bum Bae ,  Young Rak Park ,  Chi Hoon Jun ,  Seok-Hwan Moon ,  Woo-Young Jang ,  Jeong-Jin Kim ,  Hyungyu Jang ,  Je Ho Na ,  Eun Soo Nam

IPC分类号： H01L21/33 ,  H01L21/321 ,  H01L21/02 ,  H01L21/283

CPC分类号： H01L21/3212 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786

摘要： Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

摘要翻译： 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。

公开(公告)号：US09136347B2

公开(公告)日：2015-09-15

申请号：US14311675

申请日：2014-06-23

申请人： Electronics and Telecommunications Research Institute

发明人： Young Rak Park ,  Sang Choon Ko ,  Woojin Chang ,  Jae Kyoung Mun ,  Sung-Bum Bae

IPC分类号： H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/49 ,  H01L29/417 ,  H01L29/778 ,  H01L29/737

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/737 ,  H01L29/778 ,  H01L29/7786

摘要： Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.

摘要翻译： 提供一种氮化物半导体器件，包括：具有通孔的衬底; 顺序堆叠在基板上的第一和第二氮化物半导体层; 设置在第二氮化物半导体层上的漏电极和源电极; 以及设置在所述第二氮化物半导体层上的绝缘图案，所述绝缘图案具有设置在所述漏电极上的上通孔，所述贯通通孔延伸到所述第一氮化物半导体层和所述第二氮化物半导体层中，并暴露出每个所述源电极的底部 。