公开(公告)号：US20140353843A1

公开(公告)日：2014-12-04

申请号：US13909301

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： GuoXiang NING ,  Xiang HU ,  Sarasvathi THANGARAJU ,  Paul ACKMANN

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via.

Abstract translation: 电路结构和制造方法在例如第一金属水平和导电结​​构的接触表面之间提供增强的电连接。 使用多个不同尺寸的接触通孔实现增强的电连接，并且设置在接触表面上并电耦合到接触表面。 不同尺寸的接触通孔包括设置在接触表面的中心区域上的至少一个中心区域接触孔，以及设置在接触表面的周边区域上的至少一个周边区域接触孔，其中该至少一个中心区域接触 通孔大于至少一个周边区域接触通孔。

公开(公告)号：US20140370447A1

公开(公告)日：2014-12-18

申请号：US14475967

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Guoxiang NING ,  Chunyu WONG ,  Paul ACKMANN ,  Sarasvathi THANGARAJU

IPC: G03F1/26 ,  G03F7/20

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

Abstract translation: 公开了一种掩模，其包括设置在掩模的第一侧上的多个第一相移区域和设置在掩模的第二侧上的多个第二相移区域。 第一相移区域和第二相移区域可以是交变相移区域，其中第一相移区域的相移与第二相移区域的相移相异，例如180度。 还公开了一种形成掩模的方法和使用该掩模的半导体器件制造方法。

公开(公告)号：US20160328511A1

公开(公告)日：2016-11-10

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: G06F17/50 ,  H01L23/522

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Abstract translation: 公开了在IC设计的布局中所选择的区域（例如，包括关键区域）的识别和部分重新路由的方法以及所得到的设备。 实施例包括将IC器件的设计数据与制造IC器件的制造工艺标准进行比较; 在设计数据中，至少部分地基于所述布局区域中的金属段，互连段或其组合的接近来识别布局区域; 在所述布局区域中执行部分重路由以基本上满足所述准则，其中至少一个互连元件被移位或扩展; 并将部分重新路由集成到用于制造过程中的设计数据中。

公开(公告)号：US20150278426A1

公开(公告)日：2015-10-01

申请号：US14228611

申请日：2014-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Guido UEBERREITER ,  Lloyd C. LITT ,  Paul ACKMANN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract translation: 提供了一种用于电路结构的度量图案布局，包括多个象限的计量图案布局，其中象限第一晶片测量图案，第二晶片测量图案，标线片配准图案和标线片测量图案可以布置成 有助于光栅测量数据与晶圆计量数据的相关性。 标线片配准图案还可以包括被设计成保护掩模版测量图案内的其它结构元件的一个或多个最外面的结构元件在光学邻近校正过程中被修改。 提供了一种光学邻近校正处理方法，其中可以获得分划板测量图案并将其分类以添加或修改光学邻近校正处理的规则集。

公开(公告)号：US20150017803A1

公开(公告)日：2015-01-15

申请号：US13939322

申请日：2013-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Xiang HU ,  Paul ACKMANN ,  Sarasvathi THANGARAJU

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.

Abstract translation: 通过（TSV）结构制造贯穿衬底通过以下方式促进：在衬底内形成至少一个应力缓冲液; 通过所述衬底内的接触形成贯通衬底，其中所述贯通衬底通孔结构和所述应力缓冲器被设置为彼此相邻或接触; 并且其中所述应力缓冲器包括配置或者被布置在相对于所述贯通基板通孔导体的位置处，至少部分地根据所述TSV结构是否是隔离的TSV结构，链接的TSV结构或 至少部分地基于TSV结构的类型来定义通过基于导体的贯穿衬底的应力缓冲器的应力缓解。

公开(公告)号：US20170186687A1

公开(公告)日：2017-06-29

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  G03F1/36

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US20160196381A1

公开(公告)日：2016-07-07

申请号：US15071890

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Guido UEBERREITER ,  Llyod C. LITT ,  Paul ACKMANN

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

公开(公告)号：US20150287651A1

公开(公告)日：2015-10-08

申请号：US14243491

申请日：2014-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Chan Seob CHO ,  Paul ACKMANN ,  Jung Yu HSIEH ,  Hui Peng KOH

IPC: H01L21/66 ,  H01L21/306 ,  H01L27/088 ,  H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3212 ,  H01L22/12 ,  H01L27/088 ,  H01L29/4916 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.

Abstract translation: 提供了基于覆盖标记的形状和所得到的装置在有源层区域上形成虚拟结构和覆盖标记保护区域的方法。 实施例包括确定重叠标记的尺寸和形状; 基于覆盖标记的形状确定覆盖标记保护区的大小和形状; 基于重叠标记的形状确定多个虚拟结构的形状; 基于覆盖标记和多个虚拟结构的尺寸和形状来确定活动层区域的尺寸和形状; 在半导体衬底的有源层中形成有源层区; 在所述半导体衬底的多晶硅层中的所述有源层区域上形成所述覆盖标记和所述多个虚设结构; 并平坦化多层。

公开(公告)号：US20140162176A1

公开(公告)日：2014-06-12

申请号：US13710498

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Guoxiang NING ,  Chunyu WONG ,  Paul ACKMANN ,  Sarasvathi THANGARAJU

IPC: G03F1/26

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

公开(公告)号：US20200235002A1

公开(公告)日：2020-07-23

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Yuping REN ,  Paul ACKMANN ,  Guoxiang NING

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.