公开(公告)号：US09159630B1

公开(公告)日：2015-10-13

申请号：US14330063

申请日：2014-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae Geun Yang ,  Dae-han Choi

IPC: H01L21/336 ,  H01L29/76 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L27/0924

Abstract: Approaches for providing a single spacer, double hardmask dual-epi FinFET are disclosed. Specifically, at least one approach for providing the FinFET includes: forming a set of spacers along each sidewall of a plurality of fins of the FinFET device; forming a first ultra-thin hardmask over the plurality of fins; implanting the first ultra-thin hardmask over a first set of fins from the plurality of fins; removing the first ultra-thin hardmask over a second set of fins from the plurality of fins untreated by the implant; forming an epitaxial (epi) layer over the second set of fins; forming a second ultra-thin hardmask over the FinFET device; implanting the second ultra-thin hardmask; removing the second ultra-thin hardmask over the first set of fins; and growing an epi layer over the first set of fins.

Abstract translation: 公开了用于提供单个间隔物，双重硬掩模双外延FinFET的方法。 具体地，用于提供FinFET的至少一种方法包括：沿着FinFET器件的多个鳍片的每个侧壁形成一组间隔物; 在所述多个翅片上形成第一超薄硬掩模; 将第一超薄硬掩模从多个翅片植入第一组翼片; 在未被植入物处理的多个翅片上从第二组翅片上移除第一超薄硬掩模; 在所述第二组翅片上形成外延（epi）层; 在FinFET器件上形成第二个超薄硬掩模; 植入第二超薄硬掩模; 在第一组翅片上移除第二超薄硬掩模; 并在第一组翅片上生长一个外延层。

公开(公告)号：US09105478B2

公开(公告)日：2015-08-11

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei ,  Mariappan Hariharaputhiran ,  Dae Geun Yang ,  Dae-Han Choi ,  Xiang Hu ,  Richard J. Carter ,  Akshey Sehgal

IPC: H01L21/302 ,  H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US09196499B2

公开(公告)日：2015-11-24

申请号：US14225542

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L21/475 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

Abstract translation: 本发明的实施例提供了从finFET去除翅片部分的方法。 在起始点，高K电介质层设置在基板上。 翅片硬掩模和光刻叠层沉积在高k电介质上。 翅片硬掩模被暴露，并且鳍状硬标记的第一部分被去除。 去除光刻叠层。 拆下散热片硬掩模的第二部分。 鳍形成。 间隙填充电介质被沉积并凹进。

公开(公告)号：US20150270175A1

公开(公告)日：2015-09-24

申请号：US14219059

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Andy Chih-Hung Wei ,  Dae-han Choi ,  Mariappan Hariharaputhiran ,  Weihua Tong ,  Dae Geun Yang ,  Akshey Sehgal ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/268 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66795

Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.

Abstract translation: 本文提供了使用部分结晶的翅片硬掩模形成鳍状场效应晶体管（FinFET）器件的方法。 具体地说，将硬掩模图案化在衬底上，并且FinFET器件被退火以形成与一组非结晶硬掩模元件相邻的一组结晶的硬掩模元件。 在图案化的硬掩模的第一部分上提供掩模结构，以防止在退火期间该组非结晶硬掩模元件结晶。 在随后的翅片切割过程中，除去未结晶的掩模元件，同时保留结晶的掩模元件。 然后根据结晶化掩模元件的位置在FinFET器件中形成一组翅片。

公开(公告)号：US08936986B2

公开(公告)日：2015-01-20

申请号：US13797117

申请日：2013-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Dae Geun Yang

IPC: H01L21/336 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.

Abstract translation: 在一个示例中，本文公开的方法包括在用于第一类型的FinFET器件的至少一个第一鳍上方形成共用牺牲栅极结构，以及在第二类型的FinFET器件中形成至少一个第二鳍，其中第二类型与 并且在单个工艺操作中在牺牲栅极结构的整个周边周围形成第一侧壁间隔物。

公开(公告)号：US20160043081A1

公开(公告)日：2016-02-11

申请号：US14918012

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

公开(公告)号：US09147696B2

公开(公告)日：2015-09-29

申请号：US14043243

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Andy Wei ,  Lun Zhao ,  Dae Geun Yang ,  Jin Ping Liu ,  Tien-Ying Luo ,  Guillaume Bouche ,  Mariappan Hariharaputhiran ,  Churamani Gaire

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。

公开(公告)号：US09034767B1

公开(公告)日：2015-05-19

申请号：US14076386

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Dae-Han Choi ,  Dae Geun Yang ,  Taejoon Han ,  Andy Wei

IPC: H01L21/311 ,  H01L21/30 ,  H01L21/308

CPC classification number: H01L21/0337

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract translation: 通过以下方式促进掩模图案形成：提供掩模结构，其包括设置在基板结构上方的至少一个牺牲间隔结构; 将掩模层保形地设置在掩模结构上; 选择性地去除间隔层，至少部分地留下沿着至少一个牺牲间隔结构的侧壁的侧壁间隔物，并且在衬底结构上方提供至少一个额外的牺牲间隔物，该至少一个额外的牺牲隔离物 间隔件与所述至少一个牺牲间隔结构设置成间隔开的关系; 以及去除所述至少一个牺牲间隔结构，将所述侧壁间隔物和所述至少一个另外的牺牲隔离物留在所述衬底结构上作为掩模图案的一部分。

公开(公告)号：US08969205B2

公开(公告)日：2015-03-03

申请号：US13852496

申请日：2013-03-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： HongLiang Shen ,  Dae-Han Choi ,  Dae Geun Yang ,  Jung Yu Hsieh

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/3086 ,  H01L21/28114 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below.

Abstract translation: 制造中的中间半导体结构包括硅半导体衬底，在衬底上的氮化硅（SiN）的硬掩模和在硬掩模上的多晶硅或非晶硅的牺牲层。 牺牲层被图案化成侧壁间隔物，用于与侧壁间隔物例如可流动氧化物的组成基本上不同的填充材料的心轴。 去除心轴使得侧壁间隔件具有提供粗糙三角形形状的垂直锥形内侧壁和外侧壁。 粗糙的三角形侧壁间隔物用作硬掩模以在下面对SiN硬掩模进行图案化。

公开(公告)号：US20140273429A1

公开(公告)日：2014-09-18

申请号：US13797117

申请日：2013-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Dae Geun Yang

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.

Abstract translation: 在一个示例中，本文公开的方法包括在用于第一类型的FinFET器件的至少一个第一鳍上方形成共用牺牲栅极结构，以及在第二类型的FinFET器件中形成至少一个第二鳍，其中第二类型与 并且在单个工艺操作中在牺牲栅极结构的整个周边周围形成第一侧壁间隔物。