公开(公告)号：US20200044029A1

公开(公告)日：2020-02-06

申请号：US16052140

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Jody Fronheiser ,  El Mehdi Bazizi ,  Yi Qi

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L29/165 ,  H01L21/84 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

公开(公告)号：US10283642B1

公开(公告)日：2019-05-07

申请号：US15957072

申请日：2018-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  Luca Pirro

IPC: H01L29/786 ,  H01L29/08

Abstract: Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.

公开(公告)号：US10283584B2

公开(公告)日：2019-05-07

申请号：US15277583

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  Andrei Sidelnicov ,  El Mehdi Bazizi

IPC: H01L29/78 ,  H01L49/02 ,  H01L23/535 ,  H01L29/94

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.

公开(公告)号：US09881841B2

公开(公告)日：2018-01-30

申请号：US15074483

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L21/268 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

公开(公告)号：US20170047336A1

公开(公告)日：2017-02-16

申请号：US14918048

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Sven Beyer ,  Tom Herrmann ,  El Mehdi Bazizi

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.

Abstract translation: 半导体结构包括设置在半导体材料中的包括源极区，沟道区和漏极区的非易失性存储单元。 沟道区域包括邻近源极区域的第一部分和沟道区域的第一部分与漏极区域之间的第二部分。 在沟道区域的第一部分之上提供电绝缘的浮动栅极。 非易失性存储单元还包括选择栅极和控制栅极。 选择栅极的第一部分设置在沟道区域的第二部分上。 选择栅极的第二部分设置在与选择栅极的第一部分相邻的浮置栅极的一部分上。 控制栅极设置在浮动栅极上并且邻近选择栅极的第二部分。

公开(公告)号：US20160204038A1

公开(公告)日：2016-07-14

申请号：US15074483

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L21/268 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供在半导体衬底上形成的具有n沟道栅极叠层和p沟道栅叠层的结构。 该方法包括在邻近p沟道栅极叠层的半导体衬底中形成卤素注入区，并在邻近p沟道栅叠层的半导体衬底中形成延伸注入区。 该方法还包括使邻近p沟道栅叠层的卤素注入区域和半导体衬底中的延伸注入区域退火。 此外，该方法在邻近n沟道栅叠层的半导体衬底中形成延伸注入区。

公开(公告)号：US08853752B2

公开(公告)日：2014-10-07

申请号：US13661188

申请日：2012-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract translation: 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。

公开(公告)号：US10733354B2

公开(公告)日：2020-08-04

申请号：US16225199

申请日：2018-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hojin Kim ,  Dongyue Yang ,  Dong-Ick Lee ,  Yue Zhou ,  Jae Ho Joung ,  Gregory Costrini ,  El Mehdi Bazizi ,  Dongsuk Park

IPC: G06F30/398

Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.

公开(公告)号：US10121846B1

公开(公告)日：2018-11-06

申请号：US15620923

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  John Morgan

IPC: H01L49/02 ,  H01L27/06

Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.

公开(公告)号：US20140117417A1

公开(公告)日：2014-05-01

申请号：US13661188

申请日：2012-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract translation: 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。