公开(公告)号：US20180138308A1

公开(公告)日：2018-05-17

申请号：US15728615

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume BOUCHE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (RMG) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. An etch mask is then used to protect source/drain contact regions and enable the removal of the interlayer dielectric from outside of the protected area, e.g., between adjacent fins.

公开(公告)号：US20170278720A1

公开(公告)日：2017-09-28

申请号：US15077480

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  Guillaume BOUCHE ,  Byoung Youp KIM ,  Craig Michael CHILD, JR.

IPC: H01L21/3213

CPC classification number: H01L21/32 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

公开(公告)号：US20150214330A1

公开(公告)日：2015-07-30

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jin Ping LIU ,  Guillaume BOUCHE ,  Andy WEI ,  Lakshmanan H. VANAMURTHY ,  Cuiqin XU ,  Sridhar KUCHIBHATLA ,  Rama KAMBHAMPATI ,  Xiuyu CAI

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US20170309560A1

公开(公告)日：2017-10-26

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Jason Eugene STEPHENS ,  Tuhin GUHA NEOGI ,  Kai SUN ,  Deniz Elizabeth CIVAY ,  David Charles PRITCHARD ,  Andy WEI

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/5226

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20160329278A1

公开(公告)日：2016-11-10

申请号：US15134435

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Andy WEI ,  Sudharshanan RAGHUNATHAN

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.

Abstract translation: 提供了在形成后续金属层之前形成2D自对准通孔并降低所得器件和所得器件的电容的方法。 实施例包括在SiOC层中形成虚拟金属线并沿第一方向延伸; 用金属线替代虚拟金属线，每条金属线都有氮化物盖; 在氮化物盖和SiOC层上形成软掩模堆叠; 通过所述软掩模堆叠将多个通孔图形化成金属线，所述多个通孔沿着第二方向自对准; 去除软掩码堆栈; 在金属线上形成第二虚拟金属线并在第二方向上延伸; 在SiOC层上的虚拟第二金属线之间形成第二SiOC层; 并且用第二金属线代替虚拟第二金属线，第二金属线通过通孔与金属线电连接。

公开(公告)号：US20150325473A1

公开(公告)日：2015-11-12

申请号：US14275448

申请日：2014-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kisik CHOI ,  Hoon KIM ,  Andy WEI ,  Guillaume BOUCHE

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/535 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

Abstract translation: 提供了用金属 - 氧化钛触点形成半导体器件的器件和方法。 一个中间半导体器件包括例如：衬底，设置在衬底上的至少一个场效应晶体管，位于至少一个场效应晶体管的至少第一部分之间的第一接触区域，位于间隔物和中间层之间 电介质和位于至少一个场效应晶体管的至少一个第二部分之间的第二接触区域在间隔物和层间电介质之间。 一种方法包括例如获得中间半导体器件并在中间半导体器件上形成至少一个接触。

公开(公告)号：US20200006112A1

公开(公告)日：2020-01-02

申请号：US16568902

申请日：2019-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LICAUSI ,  Guillaume BOUCHE ,  Lars W. LIEBMANN

IPC: H01L21/74 ,  H01L27/108 ,  H01L27/088 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

公开(公告)号：US20190206787A1

公开(公告)日：2019-07-04

申请号：US15860171

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume BOUCHE ,  Lars W. LIEBMANN

IPC: H01L23/522 ,  H01L23/538 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.

公开(公告)号：US20180294267A1

公开(公告)日：2018-10-11

申请号：US15481826

申请日：2017-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LICAUSI ,  Guillaume BOUCHE ,  Lars W. LIEBMANN

IPC: H01L27/108 ,  H01L27/088 ,  H01L27/092 ,  H01L21/74

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

公开(公告)号：US20180174896A1

公开(公告)日：2018-06-21

申请号：US15800551

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas Vincent LICAUSI ,  Guillaume BOUCHE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286

Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.