公开(公告)号：US09159661B2

公开(公告)日：2015-10-13

申请号：US14083797

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L23/58 ,  H01L23/532 ,  H01L29/772 ,  H01L29/92 ,  H01L21/20 ,  H01L23/498 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point.

Abstract translation: 提供具有紧密电接触的集成电路和用于制造这种集成电路的方法。 该方法包括在层间电介质中形成第一和第二接触，并且在第一和第二接触之间形成凹陷。 形成覆盖在层间电介质上的蚀刻掩模，并且从凹陷中点上方去除蚀刻掩模。 在凹陷中点处的层间电介质中形成中心接触。

公开(公告)号：US20140264641A1

公开(公告)日：2014-09-18

申请号：US14184826

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kai Frohberg ,  Marco Lepper ,  Katrin Reiche ,  Torsten Huisinga

IPC: H01L29/49

CPC classification number: H01L29/4175 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/05 ,  H01L29/7833 ,  H01L2224/0401 ,  H01L2924/00 ,  H01L2924/0002

Abstract: When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers.

Abstract translation: 当形成具有接触插塞的半导体器件时，其包括形成在蚀刻停止层的侧壁上的保护层以减少短路的风险，可以通过执行溅射工艺来形成保护层，以从接触区域移除材料并将去除的材料重新沉积在侧壁上 的蚀刻停止层。

公开(公告)号：US20160079086A1

公开(公告)日：2016-03-17

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/3213 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Abstract translation: 本公开提供了一种形成半导体器件的方法，包括半导体器件的栅极结构的成形，使得避免了形成硅化物之后的间隔物去除并且抑制了硅化物突出。 在本公开的一些方面，提供一种形成半导体器件的方法，其中栅极结构设置在半导体衬底的有源区上方，栅极结构包括栅电极材料和侧壁间隔物。 通过对栅极结构施加成形工艺来形成栅电极材料和侧壁间隔物中的至少一个，并且在成形栅极结构上形成硅化物部分。

公开(公告)号：US20150137385A1

公开(公告)日：2015-05-21

申请号：US14083797

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/321

CPC classification number: H01L23/49827 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point.

Abstract translation: 提供具有紧密电接触的集成电路和用于制造这种集成电路的方法。 该方法包括在层间电介质中形成第一和第二接触，并且在第一和第二接触之间形成凹陷。 形成覆盖在层间电介质上的蚀刻掩模，并且从凹陷中点上方去除蚀刻掩模。 在凹陷中点处的层间电介质中形成中心接触。

公开(公告)号：US20150076559A1

公开(公告)日：2015-03-19

申请号：US14028876

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kai Frohberg ,  Torsten Huisinga ,  Egon Ronny Pfuetzner

IPC: H01L29/165 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/165 ,  H01L21/76272 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649

Abstract: Integrated circuits with strained silicon and methods for fabricating such integrated circuits are provided. An integrated circuit includes a stack with a surface layer, an intermediate layer, and a base layer, where the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer. The surface layer and the base layer include strained silicon, where the silicon atoms are stretched beyond a normal crystalline silicon interatomic distance. The intermediate layer includes crystalline silicon germanium.

Abstract translation: 提供了具有应变硅的集成电路及其制造方法。 集成电路包括具有表面层，中间层和基底层的堆叠，其中表面层覆盖在中间层上，中间层覆盖在基底层上。 表面层和基层包括应变硅，其中硅原子被拉伸超过正常晶体硅原子间距离。 中间层包括晶体硅锗。

公开(公告)号：US09761689B2

公开(公告)日：2017-09-12

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

公开(公告)号：US09590056B2

公开(公告)日：2017-03-07

申请号：US14967983

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kai Frohberg ,  Marco Lepper ,  Katrin Reiche

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/78 ,  H01L23/485 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L29/4175 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/05 ,  H01L29/7833 ,  H01L2224/0401 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the semiconductor layer, and a dielectric layer positioned above the etch stop layer. A contact structure that includes a conductive contact material extends through at least a portion of the dielectric layer and through an entirety of the etch stop layer to the silicide contact region, and a silicide protection layer is positioned between sidewalls of the etch stop layer and sidewalls of the contact structure.

Abstract translation: 半导体器件包括至少部分地位于半导体层中的硅化物接触区域，位于半导体层上方的蚀刻停止层以及位于蚀刻停止层上方的电介质层。 包括导电接触材料的接触结构延伸穿过电介质层的至少一部分，并通过整个蚀刻停止层延伸至硅化物接触区，硅化物保护层位于蚀刻停止层的侧壁和侧壁 的接触结构。

公开(公告)号：US20160099321A1

公开(公告)日：2016-04-07

申请号：US14967983

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kai Frohberg ,  Marco Lepper ,  Katrin Reiche

IPC: H01L29/417 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L29/4175 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/05 ,  H01L29/7833 ,  H01L2224/0401 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the semiconductor layer, and a dielectric layer positioned above the etch stop layer. A contact structure that includes a conductive contact material extends through at least a portion of the dielectric layer and through an entirety of the etch stop layer to the silicide contact region, and a silicide protection layer is positioned between sidewalls of the etch stop layer and sidewalls of the contact structure.

Abstract translation: 半导体器件包括至少部分地位于半导体层中的硅化物接触区域，位于半导体层上方的蚀刻停止层以及位于蚀刻停止层上方的电介质层。 包括导电接触材料的接触结构延伸穿过电介质层的至少一部分，并通过整个蚀刻停止层延伸至硅化物接触区，硅化物保护层位于蚀刻停止层的侧壁和侧壁 的接触结构。

公开(公告)号：US09196684B2

公开(公告)日：2015-11-24

申请号：US14254710

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Frohberg ,  Peter Moll ,  Dominik Olligs ,  Heike Scholz

IPC: H01L21/8238 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7843

Abstract: A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.

Abstract translation: 公开了一种减少FEoL地形对双应力衬垫沉积物的影响的方法和所得到的装置。 实施例包括在pFET和nFET之间和之上形成第一氮化物层; 使第一氮化物层变薄; 在所述第一氮化物层上形成第二氮化物层; 以及从pFET上方去除第一和第二氮化物层。

公开(公告)号：US20130084703A1

公开(公告)日：2013-04-04

申请号：US13687877

申请日：2012-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Frohberg ,  Frank Feustel ,  Thomas Werner

IPC: H01L21/02

CPC classification number: H01L21/02107 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7843 ,  H01L29/785

Abstract: In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.

Abstract translation: 在复杂的半导体器件中，通过在对应的晶体管之间提供间隙或应力去耦合区域，可以在紧密堆积的器件区域的相邻晶体管元件之间实现有效的应力去耦合。 例如，可以在应力诱导材料中形成间隙，以便减小紧密间隔的晶体管元件上的应力诱导材料的相互作用。 在一些说明性方面，应力诱导材料可以作为每个单独的晶体管元件的岛来提供。