公开(公告)号：US10746925B2

公开(公告)日：2020-08-18

申请号：US15878025

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Yusheng Bian

IPC: G02B5/18 ,  G02B6/124 ,  G02B6/136 ,  G02B6/132 ,  G02B6/30 ,  G02B6/12

Abstract: Grating couplers and methods of fabricating a grating coupler. The grating coupler may include a plurality of grating structures arranged on a substrate and a layer arranged over the grating structures. The grating structures are composed of a first material characterized by a first refractive index with a real part. The layer is composed of a second material characterized by a second refractive index with a real part. The real part of the second refractive index is greater than the real part of the first refractive index of the first material for electromagnetic radiation with a wavelength in a range of 1 micron to 9 microns.

公开(公告)号：US20190058002A1

公开(公告)日：2019-02-21

申请号：US15680948

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob ,  Srinivasa Banna ,  Deepak Nayak

IPC: H01L27/15 ,  H01L33/06 ,  H01L33/32 ,  H01L33/60 ,  H01L33/24 ,  H01L33/00

CPC classification number: H01L27/153 ,  H01L29/785 ,  H01L33/007 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32 ,  H01L33/502 ,  H01L33/504 ,  H01L33/60 ,  H01L2933/0041 ,  H01L2933/0058

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.

公开(公告)号：US10199429B2

公开(公告)日：2019-02-05

申请号：US15901850

申请日：2018-02-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srinivasa Banna ,  Deepak Nayak ,  Ajey P. Jacob

IPC: H01L21/00 ,  H01L27/15 ,  H01L33/06 ,  H01L33/16 ,  H01L33/32 ,  H01L33/12 ,  H01L33/62 ,  H01L33/20 ,  H01L33/00 ,  H01L33/24

Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1-xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1-xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1-xN layer in the red LED, the green LED and the blue LED.

公开(公告)号：US10056331B2

公开(公告)日：2018-08-21

申请号：US15724563

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Suraj K. Patil ,  Min-hwa Chi

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US20160293706A1

公开(公告)日：2016-10-06

申请号：US15186632

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi semiconductor material is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers. A fin extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. A stressed material is positioned in a channel cavity located below the fin, above the substrate, and laterally between the epi semiconductor material, the stressed material having a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.

Abstract translation: FinFET器件包括衬底，位于衬底上方的栅极结构以及邻近栅极结构定位的侧壁间隔物。 外延半导体材料位于FinFET器件的源极和漏极区域中，并且横向在侧壁间隔物的外侧。 翅片在FinFET器件的栅极长度方向上在栅极结构和侧壁间隔物之下横向延伸，其中鳍片的端面抵靠并接合外延半导体材料。 应力材料定位在位于翅片下方的衬底上方的通道腔中，并且横向地位于外延半导体材料之间，受压材料具有邻接并接合翅片的底表面的顶表面，邻接的底表面和 接合基板以及邻接和接合外延半导体材料的端面。

公开(公告)号：US09412822B2

公开(公告)日：2016-08-09

申请号：US14200737

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.

Abstract translation: 所公开的一种方法包括用蚀刻停止材料覆盖初始翅片结构的顶表面和侧壁的一部分，围绕初始翅片结构形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物， 去除牺牲栅极结构，其中蚀刻停止材料就位，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺，以移除位于替换下方的鳍结构的半导体衬底材料的一部分 门腔不被蚀刻停止材料覆盖，从而限定最终的翅片结构和位于最终翅片结构下方的通道腔，并且用应力材料基本上填充通道腔。

公开(公告)号：US20160111491A1

公开(公告)日：2016-04-21

申请号：US14983329

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Min-Hwa Chi

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin defined on a substrate and a gate electrode structure formed above the fin. A channel region of the device is defined beneath the gate electrode structure and source/drain regions of the fin are defined adjacent the gate electrode structure. A dielectric layer is defined at least in the channel region. The dielectric layer includes oxygen and at least one of nitrogen, carbon or fluorine.

Abstract translation: 半导体器件包括限定在衬底上的翅片和形成在鳍片上方的栅电极结构。 器件的沟道区域被限定在栅极电极结构的下方，鳍的源极/漏极区域被限定为邻近栅电极结构。 至少在通道区域中限定介电层。 介电层包括氧和氮，碳或氟中的至少一种。

公开(公告)号：US09263587B1

公开(公告)日：2016-02-16

申请号：US14476830

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Min-Hwa Chi

IPC: H01L21/265 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L29/16 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L29/0638 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming an ion implant layer in a fin defined on a semiconductor substrate. The semiconductor substrate is annealed to convert the ion implant layer to a dielectric layer. A gate electrode structure is formed above the fin in a channel region after forming the ion implant layer. The fin is recessed in a source/drain region. A semiconductor material is epitaxially grown in the source/drain region.

Abstract translation: 一种方法包括在限定在半导体衬底上的翅片上形成离子注入层。 将半导体衬底退火以将离子注入层转换成电介质层。 在形成离子注入层之后的沟道区域中，在鳍的上方形成栅电极结构。 鳍片凹陷在源极/漏极区域中。 在源极/漏极区域中外延生长半导体材料。

公开(公告)号：US09214553B2

公开(公告)日：2015-12-15

申请号：US14200952

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 所公开的一种方法包括形成由衬底，第一外延半导体材料和第二外延半导体材料的部分组成的初始鳍结构，形成绝缘材料层，从而过度填充限定 翅片，使一层绝缘材料凹陷，使得最终翅片结构的第二外延半导体部分的一部分（但不是全部）暴露，围绕最终翅片结构形成栅极结构，进一步使绝缘材料层凹陷，使得 第一外延半导体材料被暴露，去除第一外延半导体材料，从而限定下鳍腔，并用受压材料基本上填充底鳍腔。

公开(公告)号：US10263151B2

公开(公告)日：2019-04-16

申请号：US15680977

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob ,  Srinivasa Banna ,  Deepak Nayak

IPC: H01L27/15 ,  H01L33/24 ,  H01L33/40 ,  H01L21/20 ,  H01L33/18 ,  H01L33/38 ,  H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/46 ,  H01L33/36 ,  H01L33/16

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.