公开(公告)号：US20180083136A1

公开(公告)日：2018-03-22

申请号：US15268796

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Steven J. Bentley ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L21/30604 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666

Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.

公开(公告)号：US09716174B2

公开(公告)日：2017-07-25

申请号：US13945455

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795

Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET. The oxidized sacrificial layer under the active channel prevents punch-through leakage in the final FinFET structure.

公开(公告)号：US09536990B2

公开(公告)日：2017-01-03

申请号：US14727458

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/7846 ,  H01L29/7848

Abstract: One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height for a replacement fin, performing an etching process through the patterned fin etch mask to form a plurality of trenches in a semiconductor substrate to define a substrate fin and forming a recessed layer of insulating material in the trenches so as to expose the patterned fin etch. The method also includes forming a layer of CTE-matching material around the exposed patterned fin etch mask, removing the patterned fin etch mask to thereby define a replacement fin cavity and expose a surface of the substrate fin, forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种方法包括形成具有等于或大于用于替换翅片的目标最终翅片高度的厚度的图案化翅片，通过图案化翅片蚀刻掩模执行蚀刻工艺以形成多个沟槽 在半导体衬底中限定衬底鳍并在沟槽中形成绝缘材料的凹陷层，以暴露图案化鳍片蚀刻。 该方法还包括在暴露的图案化鳍状物蚀刻掩模周围形成CTE匹配材料层，去除图案化的鳍状蚀刻掩模，从而限定替换的翅片腔并暴露衬底鳍片的表面，在衬底鳍片上形成置换鳍片 并且在替换翅片腔中，去除CTE匹配材料层并在替换翅片的至少一部分周围形成栅极结构。

公开(公告)号：US09508853B2

公开(公告)日：2016-11-29

申请号：US15073936

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201 ,  H01L21/306 ,  H01L29/10 ,  H01L29/51

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括围绕初始鳍片的一部分形成牺牲栅极结构，在牺牲栅极结构的相对侧上形成侧壁间隔物，并去除牺牲栅极 结构，从而限定替换栅极腔，通过替代栅极腔执行蚀刻工艺以去除初始翅片的部分，从而限定在侧壁间隔物下方的减小尺寸的翅片和凹陷，形成至少一个替代外延半导体 在更换的浇口腔体和侧壁间隙的凹槽内围绕减小尺寸的翅片的覆层材料，以及在至少一个替代的外延半导体包层材料周围的置换栅极腔内形成替换栅极结构。

公开(公告)号：US20160126353A1

公开(公告)日：2016-05-05

申请号：US14526617

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Yi Qi ,  Sylvie Mignot

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/02 ,  H01L21/324 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/324 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract translation: 一种方法包括在半导体衬底上形成翅片并在翅片的侧壁上形成凹槽。 凹槽中形成硅合金材料。 进行热处理以从硅合金材料和翅片限定硅合金翅片部分。 半导体器件包括衬底，限定在衬底上的翅片和邻近翅片设置的隔离结构。 在隔离结构上方延伸的翅片的第一部分具有基本上垂直的侧壁和不同于在隔离结构上方延伸的翅片的第二部分的不同材料组成。

公开(公告)号：US20150214369A1

公开(公告)日：2015-07-30

申请号：US14164934

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Bharat V. Krishnan ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Ajey Poovannummoottil Jacob ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L29/26 ,  H01L29/04 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/26 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract translation: 本文公开的一种说明性器件包括在具有晶体结构的半导体衬底中限定的鳍，其中鳍的至少一个侧壁基本上位于衬底的100°结晶方向，位于鳍周围的栅极结构， 侧壁间隔物，其位于栅极结构的相对侧附近，以及外延半导体材料，其围绕位于器件的源极/漏极区域中的最外侧壁间隔物横向外侧的翅片周围形成，其中外延半导体材料具有基本上均匀的厚度 沿翅片的侧壁。

公开(公告)号：US09960257B2

公开(公告)日：2018-05-01

申请号：US14656671

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545

Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.

公开(公告)号：US20170179127A1

公开(公告)日：2017-06-22

申请号：US14974136

申请日：2015-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Shogo Mochizuki ,  Stephen W. Bedell

IPC: H01L27/092 ,  H01L29/15 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/155 ,  H01L29/66795

Abstract: An aspect of the disclosure includes a semiconductor structure comprising: a set of fins on a substrate, the set of fins including a relaxed silicon germanium layer; and a dielectric between each fin in the set of fins; wherein each fin in a n-type field effect transistor (nFET) region further includes a strained silicon layer over the relaxed silicon germanium layer of each fin in the nFET region; wherein each fin in a p-type field effect transistor (pFET) region further includes a strained silicon germanium layer over the relaxed silicon germanium layer of each fin in the pFET region.

公开(公告)号：US09502507B1

公开(公告)日：2016-11-22

申请号：US15012107

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/283 ,  H01L21/306 ,  H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, removing at least a portion of a vertical height of portions of an overall fin structure that are not covered by a gate structure so as to result in the definition of a fin cavity in a layer of insulating material and the definition of a remaining portion of the overall fin structure that is positioned under the gate structure, wherein the remaining portion comprises a channel portion and a lower portion located under the channel portion. The method continues with the formation of a first semiconductor material within at least the fin cavity and the formation of a second semiconductor material on the first semiconductor material and on exposed edges of the channel portion.

Abstract translation: 本文公开的一种说明性方法包括除去未被栅极结构覆盖的整个鳍结构的部分的垂直高度的至少一部分，以便导致在一层中的翅片腔的定义 绝缘材料和定位在栅极结构下方的整个鳍结构的剩余部分的定义，其中剩余部分包括通道部分和位于通道部分下方的下部分。 该方法继续在至少翅片腔内形成第一半导体材料，并在第一半导体材料上形成第二半导体材料并在通道部分的暴露边缘上形成第二半导体材料。

公开(公告)号：US20160225676A1

公开(公告)日：2016-08-04

申请号：US14608815

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/762 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L21/845 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

Abstract translation: 本文公开的一种说明性方法包括形成复合翅片结构，该复合翅片结构由具有第一锗浓度的第一含锗半导体材料和位于第一锗浓度的拉伸应变第二半导体材料（具有较小的锗浓度）组成 第一含锗半导体材料，并且进行热退火工艺以将复合翅片结构的第一含锗半导体材料部分转换成位于第二半导体材料下方的含锗氧化物隔离区域，该第一半导体材料是拉伸应变末端鳍 用于NMOS FinFET器件。