公开(公告)号：US10249502B2

公开(公告)日：2019-04-02

申请号：US15004751

申请日：2016-01-22

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/336 ,  H01L21/285 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US09431534B2

公开(公告)日：2016-08-30

申请号：US14557541

申请日：2014-12-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L21/845 ,  H01L21/26586 ,  H01L21/31111 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: A device includes a field effect transistor on an insulating film. A first fin extends vertically from a top side of a horizontal surface of a semiconductor substrate. An epitaxial cap rests on the first fin, with a left vertex on a left side of the epitaxial cap at a first horizontal distance from a reference line that vertically bisects the first fin, and a right vertex on the right side of the epitaxial cap at a second horizontal distance from the reference line, the first horizontal distance being at least twenty percent greater than the second horizontal distance; and a top vertex is at a third horizontal distance to the left of the reference line.

Abstract translation: 一种器件包括在绝缘膜上的场效应晶体管。 第一鳍从半导体衬底的水平表面的顶侧垂直延伸。 外延帽位于第一鳍片上，在外延帽的左侧的左顶点与从垂直方向平分第一鳍片的基准线和第二鳍片的右侧的右顶点处的第一水平距离处 距离参考线的第二水平距离，第一水平距离比第二水平距离大至少20％; 并且顶部顶点距离参考线左侧的第三水平距离。

公开(公告)号：US09349661B2

公开(公告)日：2016-05-24

申请号：US14161738

申请日：2014-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hanyi Ding ,  Oleg Gluschenkov ,  Ping-Chuan Wang ,  Lin Zhou

IPC: H01L21/78 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/30625 ,  H01L21/76898 ,  H01L22/14

Abstract: Embodiments of the present invention provide an apparatus and method for wafer thinning endpoint detection. Embodiments of the present invention utilize through silicon via (TSV) structures formed in the wafer. A specially made wafer handle is bonded to the wafer. Conductive slurry is used in the wafer backside thinning process. The wafer handle provides electrical connectivity to an electrical measurement tool, and conductive posts in the wafer handle are proximal to a test structure on the wafer. A plurality of electrically isolated TSVs is monitored via the electrical measurement tool. When the TSVs are exposed on the backside as a result of thinning, the conductive slurry shorts the electrically isolated TSVs, changing the electrical properties of the plurality of TSVs. The change in electrical properties is detected and used to trigger termination of the wafer backside thinning process.

Abstract translation: 本发明的实施例提供了一种用于晶片薄化端点检测的装置和方法。 本发明的实施例利用在晶片中形成的硅通孔（TSV）结构。 特殊制造的晶圆把手与晶片结合。 导电浆料用于晶片背面变薄处理。 晶片手柄提供与电测量工具的电连接，并且晶片把手中的导电柱靠近晶片上的测试结构。 通过电测量工具监测多个电隔离TSV。 当TSV由于变薄而暴露在背面时，导电浆料使电隔离的TSV短路，改变多个TSV的电性能。 检测电特性的变化并用于触发晶圆背面变薄过程的终止。

公开(公告)号：US10109722B2

公开(公告)日：2018-10-23

申请号：US15447210

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Zhenxing Bi ,  Pietro Montanini ,  Eric R. Miller ,  Balasubramanian Pranatharthiharan ,  Oleg Gluschenkov ,  Ruqiang Bao ,  Kangguo Cheng

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/3105

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.

公开(公告)号：US09905692B2

公开(公告)日：2018-02-27

申请号：US15160099

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Shogo Mochizuki ,  Veeraraghavan S. Basker ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.

公开(公告)号：US09679810B1

公开(公告)日：2017-06-13

申请号：US15041203

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US09412658B2

公开(公告)日：2016-08-09

申请号：US14490792

申请日：2014-09-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

公开(公告)号：US11562906B2

公开(公告)日：2023-01-24

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US20190181012A1

公开(公告)日：2019-06-13

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/24 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L29/267

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US20180254331A1

公开(公告)日：2018-09-06

申请号：US15447210

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Zhenxing Bi ,  Pietro Montanini ,  Eric R. Miller ,  Balasubramanian Pranatharthiharan ,  Oleg Gluschenkov ,  Ruqiang Bao ,  Kangguo Cheng

IPC: H01L29/66 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/3105 ,  H01L21/31053 ,  H01L29/6656

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.