公开(公告)号：US09406545B2

公开(公告)日：2016-08-02

申请号：US14735466

申请日：2015-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L27/108 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/7621 ,  H01L21/76205 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851

Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.

公开(公告)号：US09236463B2

公开(公告)日：2016-01-12

申请号：US14027563

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/10 ,  H01L29/205 ,  H01L29/20 ,  H01L29/51

CPC classification number: H01L29/778 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/205 ,  H01L29/4232 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

公开(公告)号：US09728649B2

公开(公告)日：2017-08-08

申请号：US15009906

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

公开(公告)号：US09673296B2

公开(公告)日：2017-06-06

申请号：US14937029

申请日：2015-11-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC: H01L29/76 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/84 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/78

Abstract: A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.

公开(公告)号：US20160163879A1

公开(公告)日：2016-06-09

申请号：US15009906

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种半导体器件。 半导体器件可以包括设置在衬底上的第一介电层; 设置在所述第一电介质层上的一组偏置线; 第二电介质层，设置在所述第一电介质层上和所述一组偏置线之间，其中所述第二电介质层的厚度小于所述第一介电层的厚度; 设置在所述第二电介质层的部分上的图案化半导体层; 以及设置在所述偏置线组之上的图案化半导体层上的一组器件。

公开(公告)号：US09330908B2

公开(公告)日：2016-05-03

申请号：US13925911

申请日：2013-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L21/8258 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L21/02538 ,  H01L21/02373 ,  H01L21/02441 ,  H01L21/02447 ,  H01L21/02494 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/088

Abstract: A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance.

Abstract translation: 半导体结构包括第一半导体区域。 第一半导体区域包括由具有顶表面和后表面的IV族半导体材料组成的第一半导体层。 第一半导体层在顶表面具有至少大于纵横比捕获（ART）距离的深度的开口。 第一半导体区域还具有由沉积在第一半导体层的开口内和顶表面上的III / V族半导体化合物构成的第二半导体层。 第二半导体层从开口的底部到ART距离形成ART区域。

公开(公告)号：US09281198B2

公开(公告)日：2016-03-08

申请号：US13900808

申请日：2013-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L21/28 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种形成半导体器件的方法。 该方法包括在基底上形成第一介电层; 在所述第一电介质层上形成一组偏置线; 用第二电介质层覆盖该组偏置线; 在所述第二电介质层上形成半导体层; 以及在所述偏置线组之上的半导体层上形成一组器件。

公开(公告)号：US08809920B2

公开(公告)日：2014-08-19

申请号：US13670674

申请日：2012-11-07

Applicant: International Business Machines Corporation ,  GlobalFoundries Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/76

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US09401373B2

公开(公告)日：2016-07-26

申请号：US14641462

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate.

公开(公告)号：US09362310B2

公开(公告)日：2016-06-07

申请号：US14694243

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/167 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors.