公开(公告)号：US10680065B2

公开(公告)日：2020-06-09

申请号：US16052140

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Jody Fronheiser ,  El Mehdi Bazizi ,  Yi Qi

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L29/165 ,  H01L21/84 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/786

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

公开(公告)号：US20190043944A1

公开(公告)日：2019-02-07

申请号：US15667376

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Matthew W. Stoker ,  Judson R. Holt ,  Timothy J. McArdle ,  Annie Lévesque

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/02 ,  H01L29/49 ,  H01L29/423

Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.

公开(公告)号：US10236343B2

公开(公告)日：2019-03-19

申请号：US15848591

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina H. Triyoso ,  Timothy J. McArdle ,  Judson R. Holt ,  Amy L. Child ,  George R. Mulfinger

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

公开(公告)号：US10043893B1

公开(公告)日：2018-08-07

申请号：US15668012

申请日：2017-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Timothy J. McArdle ,  Judson Robert Holt

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L27/12

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins formed over a substrate; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a u-shaped cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each u-shaped cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

公开(公告)号：US20160181285A1

公开(公告)日：2016-06-23

申请号：US15054951

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric C.T. Harley ,  Judson R. Holt ,  Yue Ke ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.

公开(公告)号：US20160163707A1

公开(公告)日：2016-06-09

申请号：US15016612

申请日：2016-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Eric C.T. Harley ,  Judson R. Holt ,  Gauri V. Karve ,  Yue Ke ,  Derrick Liu ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa Alyson Smith

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract translation: 本发明的实施例提供了一种外延生长FinFET的方法。 一种方法可以包括提供包括绝缘体和底层的半导体衬底; 使用外延生长在所述半导体衬底上形成沟道层; 将凹槽蚀刻到沟道层中并外延地再生沟道层上的一部分; 蚀刻通道层和底层以形成翅片; 形成栅极结构和一组间隔物; 将源漏区蚀刻到沟道层中; 以及在源极漏极区域中形成源极漏极材料。

公开(公告)号：US09236250B2

公开(公告)日：2016-01-12

申请号：US13924064

申请日：2013-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Robert L. Wisnieff

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/267

CPC classification number: H01L21/02447 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02656 ,  H01L29/1606 ,  H01L29/267

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

公开(公告)号：US10741556B2

公开(公告)日：2020-08-11

申请号：US15719014

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

公开(公告)号：US10396078B2

公开(公告)日：2019-08-27

申请号：US16002070

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

公开(公告)号：US10388654B2

公开(公告)日：2019-08-20

申请号：US15868058

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  George Mulfinger ,  Timothy J. McArdle ,  Thomas Merbeth ,  Ömür Aydin ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.