公开(公告)号：US20190252530A1

公开(公告)日：2019-08-15

申请号：US16394421

申请日：2019-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L29/08 ,  H01L23/535 ,  H01L27/12 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/535 ,  H01L27/04 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7371

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US10340352B2

公开(公告)日：2019-07-02

申请号：US15458482

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Alvin J. Joseph ,  John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L21/28 ,  H01L21/265 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.

公开(公告)号：US20180323066A1

公开(公告)日：2018-11-08

申请号：US15584121

申请日：2017-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Alvin J. Joseph ,  Michael J. Zierak

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/16

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

公开(公告)号：US09570564B2

公开(公告)日：2017-02-14

申请号：US14451716

申请日：2014-08-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deborah A. Alperstein ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Keith J. Machia ,  Christa R. Willets

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 在包含第一端子的基板上形成第一半导体层。 在第一半导体层上形成蚀刻停止层，在蚀刻停止层上形成第二半导体层。 蚀刻第二半导体层以在第二半导体层上的蚀刻掩模的位置处限定第二端子。 选择包括蚀刻停止层的第一材料和包括第二半导体层的第二材料，使得第二半导体层的第二材料以比蚀刻停止层的第一材料更高的蚀刻速率蚀刻。 第一半导体层可以是用于形成双极结型晶体管的本征基极和非本征基极的基极层。

公开(公告)号：US20160372396A1

公开(公告)日：2016-12-22

申请号：US14745800

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L23/367 ,  H01L21/48 ,  H01L29/08 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L23/367 ,  H01L21/4882 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/66272 ,  H01L29/732

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

Abstract translation: 芯片封装和形成芯片封装的方法。 芯片封装包括功率放大器和构造成影响热能传输的热通路结构。 功率放大器包括第一发射器指状物和第二发射器指状物，其具有至少一个基于与热路径结构接近度选择的参数。

公开(公告)号：US10211146B2

公开(公告)日：2019-02-19

申请号：US15152794

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L27/12 ,  H01L23/482 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US10134880B2

公开(公告)日：2018-11-20

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US20170278955A1

公开(公告)日：2017-09-28

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L21/762 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/732 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20160372548A1

公开(公告)日：2016-12-22

申请号：US14745764

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/73

CPC classification number: H01L29/0813 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.

Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 形成由第一半导体材料构成的基底层。 在基底层上形成由第二半导体材料构成的发射极层。 图案化发射极层以形成发射极指状物，其长度和宽度沿着发射极指的长度而变化。

公开(公告)号：US09385022B2

公开(公告)日：2016-07-05

申请号：US14283984

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  G02B6/134 ,  G02B6/136 ,  G02B6/132 ,  G02B6/12 ,  G02B6/122

CPC classification number: H01L21/76224 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B2006/12061 ,  H01L21/762 ,  H01L29/06 ,  H01L29/0649

Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

Abstract translation: 各种方法包括：在体硅层中形成光波导，光波导包括覆盖硅衬底区域的一组浅沟槽隔离（STI）区域; 离子注入硅衬底以使硅衬底的一部分非晶化; 通过STI区域形成一组沟槽并进入下面的硅衬底区域; 底切蚀刻在STI区域下方的硅衬底区域通过该组沟槽以形成一组空穴，其中硅衬底的至少部分非晶化部分以小于硅衬底的蚀刻速率的速率蚀刻; 并密封该组腔。