公开(公告)号：US20180090574A1

公开(公告)日：2018-03-29

申请号：US15560428

申请日：2015-05-18

Applicant: HITACHI, LTD.

Inventor： Mieko MATSUMURA ,  Junichi SAKANO ,  Naoki TEGA ,  Yuki MORI ,  Haruka SHIMIZU ,  Keisuke KOBAYASHI

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L29/0615 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7802

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

公开(公告)号：US20130146897A1

公开(公告)日：2013-06-13

申请号：US13684314

申请日：2012-11-23

Applicant: Hitachi, Ltd.

Inventor： Hiroyuki YOSHIMOTO ,  Ryuta TSUCHIYA ,  Naoki TEGA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO ,  Yuki MORI

IPC: H01L29/16

CPC classification number: H01L29/1608 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7827

Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.

Abstract translation: 形成沟槽，在（0001）面4h-SiC半导体元件的沟道区的周围埋置氧化硅膜。 沟槽中的氧化膜以这样的平面布局限定，使得沿着c轴的方向施加拉伸应变，并且沿着与c轴垂直的平面上的两个或更多个轴施加压缩应变。 例如，埋置有氧化物膜的沟槽沟可以被配置为使得它们处于围绕通道的三角形状，或者当离散布置时相对于通道对称地布置为中心。

公开(公告)号：US20180350973A1

公开(公告)日：2018-12-06

申请号：US15759790

申请日：2015-09-15

Applicant: Hitachi, Ltd.

Inventor： Yuki MORI ,  Akio SHIMA

IPC: H01L29/78 ,  H02P27/06 ,  H01L29/16 ,  H01L29/167 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/04 ,  B60L15/00

CPC classification number: H01L29/7811 ,  B60L15/00 ,  B60L2200/26 ,  H01L21/0465 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7805 ,  H01L29/861 ,  H01L29/868 ,  H02P27/06

Abstract: An object of the present invention is to suppress energization deterioration due to crystal defects in a semiconductor device including SiC-MOSFET. To solve this problem, a semiconductor device of the present invention includes: an n−-type epitaxial layer formed on a main surface of an n+-type SiC substrate; a p-type termination region that is annularly formed in the n−-type epitaxial layer outside an active region; and an n-type hole annihilation region annularly formed in the n−-type epitaxial layer outside the p-type termination region, apart from the p-type termination region. Then, the n-type hole annihilation region has a first end surface facing the p-type termination region, as well as a second end surface on the opposite side of the first end surface. When a depth of the n-type hole annihilation region is dTM, a depth of the p-type termination region is dNR, a thickness of the n−-type epitaxial layer is dEpi, a distance from the first end surface of the n-type hole annihilation region to the second end surface thereof is LNR, and a distance from the first end surface of the n-type hole annihilation region to the periphery of the semiconductor substrate is |XNR|, these variables have the following relationship: dNR≤dTM, (|XNR|+dNR)≥dEpi, 0

公开(公告)号：US20160190020A1

公开(公告)日：2016-06-30

申请号：US14911651

申请日：2013-08-14

Applicant: HITACHI, LTD.

Inventor： Yoshinobu KIMURA ,  Natsuki TSUNO ,  Hiroya OHTA ,  Renichi YAMADA ,  Hirotaka HAMAMURA ,  Toshiyuki OHNO ,  Hiroyuki OKINO ,  Yuki MORI

IPC: H01L21/66 ,  G01R31/265

CPC classification number: H01L22/12 ,  G01R31/265 ,  H01L22/20 ,  H01L22/24

Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.

Abstract translation: 在使用半导体检查装置的半导体检查方法中，通过选择入射能量和负电位并扫描具有一次电子的晶片的检查表面以检测二次电子，获得第一检查图像，并且存在宏观缺陷，堆垛层错 通过基于预先确定的二次电子的信号量的阈值的图像处理来判别包含在第一检查图像中的基底位错和穿透位错。 此外，通过选择入射能量和正电位并用一次电子扫描晶片的检查表面以检测二次电子，获得第二检查图像，并且包含在第二电极中的点状图形的螺纹螺钉脱位 基于预先确定的二次电子的信号量的阈值的图像处理来判别检查图像。

公开(公告)号：US20160149025A1

公开(公告)日：2016-05-26

申请号：US14904685

申请日：2013-07-16

Applicant: HITACHI LTD.

Inventor： Yuki MORI ,  Toshiyuki MINE ,  Hiroshi MIKI ,  Mieko MATSUMURA ,  HIrotaka HAMAMURA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L29/7802 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66068

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract translation: 提供了一种在半导体器件中与Si功率MOSFET一样多地确保栅极绝缘膜的可靠性的技术，其中使用具有比硅更大的带隙的半导体材料，并且其典型例如为 一个SiC功率MOSFET。 为了实现该目的，在SiC功率MOSFET中，栅电极GE形成为与栅极绝缘膜GOX接触，并且由厚度等于或小于200nm的多晶硅膜PF1形成， 和形成为与多晶硅膜PF1接触并且具有任何厚度的多晶硅膜PF2。