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    Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device
    3.
    发明授权
    Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device 有权
    闪存器件的核心和周边区域内的STI（浅沟槽隔离）结构的形成

    公开(公告)号：US06509232B1

    公开(公告)日：2003-01-21

    申请号：US09969573

    申请日：2001-10-01

    申请人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

    发明人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.

    摘要翻译： 形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。 核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。 核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。 电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的 。 沉积沟槽电介质材料以填充STI开口。 此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。 外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。 核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

    Core array and periphery isolation technique
    4.
    发明授权
    Core array and periphery isolation technique 失效
    核心阵列和外围隔离技术

    公开(公告)号：US06004862A

    公开(公告)日：1999-12-21

    申请号：US8320

    申请日：1998-01-20

    申请人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

    发明人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76202 ,  H01L21/76224

    摘要： A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.

    摘要翻译： 一种用于形成半导体集成电路的方法，所述半导体集成电路具有密集地填充有有源器件的核心区域，并且与所述核心区域相比具有较少密集地填充有源器件的外围区域，包括以下步骤：在第一绝缘体材料的上方形成第一层 具有芯区域和周边区域的半导体衬底，其中所述第一绝缘体材料构成用于抛光工艺的抛光止挡件以及氧化屏障; 图案化第一绝缘体材料层，以在使用第一绝缘体材料基本上遮蔽周边区域的同时，在半导体衬底的基本上仅在芯部区域露出第一部分; 在芯区域中的半导体衬底的暴露的第一部分中形成多个沟槽; 用绝缘体填充多个沟槽; 抛光到第一绝缘体材料层; 去除第一绝缘体材料的第一层; 在所述芯和外围区域上形成第二绝缘体材料层; 将第一绝缘体材料的第二层向下形成开口，以便在使用第二层基本上掩蔽核心区域时，基本上只在周边区域露出半导体衬底的第二部分; 以及在半导体衬底的暴露的第二部分中形成隔离区。

    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
    7.
    发明授权
    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
    非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间

    公开(公告)号：US06664191B1

    公开(公告)日：2003-12-16

    申请号：US09973131

    申请日：2001-10-09

    申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    IPC分类号： H01L21302

    CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

    摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

    摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

    Method and system for providing a contact on a semiconductor device
    8.
    发明授权
    Method and system for providing a contact on a semiconductor device 失效
    用于在半导体器件上提供接触的方法和系统

    公开(公告)号：US6103593A

    公开(公告)日：2000-08-15

    申请号：US23836

    申请日：1998-02-13

    申请人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    发明人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/76237 ,  H01L21/76834 ,  Y10S438/97

    摘要： A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.

    摘要翻译： 公开了一种在半导体上提供至少一个接触的方法。 半导体包括多个隔离结构。 该方法和系统包括提供与半导体直接接触的蚀刻停止层，在蚀刻停止层上方提供介电层，以及蚀刻穿过介电层和蚀刻停止层的一部分。 在蚀刻期间，与多个隔离结构之一接近的半导体的一部分不暴露。

    Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device
    9.
    发明授权
    Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device 有权
    在半导体器件中形成单个互间电介质层的方法和布置

    公开(公告)号：US06433383B1

    公开(公告)日：2002-08-13

    申请号：US09357333

    申请日：1999-07-20

    申请人： Mark Ramsbey ,  Unsoon Kim ,  Kenneth Wo-Wai Au ,  David H. Chi ,  James Markarian

    发明人： Mark Ramsbey ,  Unsoon Kim ,  Kenneth Wo-Wai Au ,  David H. Chi ,  James Markarian

    IPC分类号： H01L27108

    CPC分类号： H01L27/11521 ,  H01L21/3144 ,  H01L21/3145 ,  H01L27/115 ,  H01L29/511

    摘要： A single interpoly dielectric layer is provided for use in semiconductor devices. The single interpoly dielectric layer being formed of silicon graded such that certain regions within the single interpoly dielectric layer are either oxygen-rich or nitrogen-rich. The single interpoly dielectric layer can be formed in-situ within a single deposition tool. In certain embodiments, the resulting single interpoly dielectric layer can be made thinner and/or can be formed to provide improved dielectric characteristics when compared to a conventional oxide-nitride-oxide (ONO) interpoly dielectric layer that has three separate and unique layers. Thus, the single interpoly dielectric layer is highly desirable for use in reduced-size semiconductor devices and/or semiconductor devices requiring improved data retention capabilities, such as non-volatile memory cells.

    摘要翻译： 提供了一个用于半导体器件的单互补电介质层。 由硅分级形成的单个间隔电介质层使得单个互间介电层内的某些区域是富氧或富含氮的。 单个间隔电介质层可以在单个沉积工具内原位形成。 在某些实施例中，当与具有三个独立且独特的层的常规氧化物 - 氮化物 - 氧化物（ONO）间隔电介质层相比时，所得到的单个间隔电介质层可以制成更薄和/或可形成以提供改善的介电特性。 因此，对于需要改进的数据保持能力的尺寸较小的半导体器件和/或半导体器件（例如非易失性存储器单元），单个互聚电介质层是非常需要的。