公开(公告)号：US11018235B2

公开(公告)日：2021-05-25

申请号：US15349904

申请日：2016-11-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Anabela Veloso ,  Julien Ryckaert

IPC: H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/786 ,  H01L27/11 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/06 ,  H01L29/417

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

公开(公告)号：US20180174642A1

公开(公告)日：2018-06-21

申请号：US15851531

申请日：2017-12-21

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/408 ,  H01L29/08 ,  H01L29/423

CPC classification number: G11C11/412 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected. A source/drain of the pull-up transistor and of the pull-down transistor of the second stack, a source/drain of the pass transistor of the second stack and the common gate electrode of the pull-up and pull-down transistors of the first stack are electrically interconnected.

公开(公告)号：US20210193912A1

公开(公告)日：2021-06-24

申请号：US17119010

申请日：2020-12-11

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Mohit Gupta ,  Trong Huynh Bao

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A material layer stack, a non-volatile memory device comprising the stack, and arrays thereof are described. The material layer stack comprises first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion, wherein a tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes. Preferably, a bottom face of the stack is connected to a conductor supporting current induced magnetic polarization switching for the first magnetic tunnel junction by spin-orbit torque; magnetic polarization switching for the second magnetic tunnel junction is preferably achieved by spin-transfer torque.

公开(公告)号：US20200312725A1

公开(公告)日：2020-10-01

申请号：US16836478

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234

Abstract: The disclosed technology relates to methods of fabricating field-effect transistors having channels extending in horizontal and vertical directions. According to an aspect, a method comprises: providing a semiconductor substrate comprising: in a vertical channel field-effect transistor (FET) device region, a first layer structure comprising a lower semiconductor layer, an intermediate semiconductor layer above the lower semiconductor layer and an upper semiconductor layer above the intermediate semiconductor layer, and, in a horizontal channel FET device region, a second layer structure comprising at least one semiconductor layer, wherein the first layer structure and the second layer structure have different compositions and wherein a surface of the substrate in the vertical channel FET device region is coplanar with a surface of the substrate in the horizontal channel FET device region; forming a mask defining a first semiconductor structure mask portion above the vertical channel FET device region and a second semiconductor structure mask portion above the horizontal channel FET device region; and patterning the first layer structure and the second layer structure by simultaneously etching the first layer structure and the second layer structure while using the mask as an etch mask, thereby forming: a first semiconductor structure for a vertical channel FET device in the vertical channel FET device region, the first semiconductor structure comprising a lower layer portion, an intermediate layer portion and an upper layer portion, and a second semiconductor structure for a horizontal channel FET device in the horizontal channel FET device region.

公开(公告)号：US20200211642A1

公开(公告)日：2020-07-02

申请号：US16727653

申请日：2019-12-26

Applicant: IMEC VZW

Inventor： Trong Huynh Bao ,  Sushil Sakhare

IPC: G11C13/00 ,  G11C14/00

Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

公开(公告)号：US20180330997A1

公开(公告)日：2018-11-15

申请号：US15977381

申请日：2018-05-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

公开(公告)号：US20180190670A1

公开(公告)日：2018-07-05

申请号：US15858821

申请日：2017-12-29

Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

Inventor： Julien Ryckaert ,  Trong Huynh Bao

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  B82Y10/00 ,  H01L27/0207 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2027/11816 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a standard cell semiconductor device comprising transistors having vertical channels and a common gate. In one aspect, a standard cell semiconductor device comprises a substrate, a unit cell having a first transistor and a second transistor, a gate layer common to the first and second transistor, and a set of routing tracks for contacting the first and second transistor. Each one of the first and second transistors is formed of a stack of layers arranged between at least some of the routing tracks and the substrate, wherein each stack comprises a bottom terminal arranged on the substrate, a channel arranged on the bottom terminal and a top terminal arranged on the channel. The channel of the first transistor is an N-type channel, and the channel of the second transistor is a P-type channel. Further, the routing tracks comprises a pair of power routing tracks arranged on opposite sides of the unit cell and adapted to contact the top terminal of the first and second transistors, and a gate track arranged between the pair of power routing tracks and adapted to contact the gate layer at a position beside the unit cell.

公开(公告)号：US11527709B2

公开(公告)日：2022-12-13

申请号：US17027525

申请日：2020-09-21

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Mohit Gupta ,  Trong Huynh Bao

IPC: H01L43/08 ,  G01R33/09 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10

Abstract: The disclosed technology relates to a multibit memory cell. In one aspect, the multibit memory cell includes a plurality of spin-orbit torque (SOT) tracks, plurality of magnetic tunnel junctions (MTJs), an electrically conductive path connecting a first MTJ and a second MTJ together, and a plurality of terminals. The plurality of terminals can be configured to provide a first SOT write current to the first MTJ, a second SOT write current to the second MTJ, and at least one of: the second SOT write current to a third MTJ, a third SOT write current to the third MTJ, and a spin transfer torque (STT) write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current through all the MTJs in series.

公开(公告)号：US11217488B2

公开(公告)日：2022-01-04

申请号：US16835786

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L21/311

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.

公开(公告)号：US20210098694A1

公开(公告)日：2021-04-01

申请号：US17027525

申请日：2020-09-21

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Mohit Gupta ,  Trong Huynh Bao

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  G01R33/09

Abstract: The disclosed technology relates to a multibit memory cell. In one aspect, the multibit memory cell includes a plurality of spin-orbit torque (SOT) tracks, including at least a first SOT track and a second SOT track separate from the first SOT track. The cell further includes a plurality of magnetic tunnel junctions (MTJs), including at least a first MTJ arranged on the first SOT track, and a second MTJ and a third MTJ arranged on the second SOT track. The cell further includes an electrically conductive path connecting the first MTJ and the second MTJ together, and a plurality of terminals, of which some may be optional. The plurality of terminals can be configured to provide a first SOT write current to the first MTJ, a second SOT write current to the second MTJ, and at least one of: the second SOT write current to the third MTJ, a third SOT write current to the third MTJ, and an spin transfer torque (STT) write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current through all the MTJs in series.