公开(公告)号：US20240314072A1

公开(公告)日：2024-09-19

申请号：US18417570

申请日：2024-01-19

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L45/74 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/90

CPC classification number: H04L45/742 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/9068

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20220350499A1

公开(公告)日：2022-11-03

申请号：US17745453

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Yadong LI ,  Anjali Singhai JAIN ,  Kenneth G. KEELS ,  Andrzej SAWULA ,  Kun TIAN ,  Ashok RAJ ,  Rupin H. VAKHARWALA ,  Rajesh M. SANKARAN ,  Saurabh GAYEN ,  Baolu LU ,  Yan ZHAO

IPC: G06F3/06 ,  G06F9/455

Abstract: As described herein, for a selected process identifier and virtual address, a page fault arising from multiple sources can be solved by a one-time operation. The selected process identifier can include a virtual function (VF) identifier or process address space identifier (PASID). In some examples, solving a page fault arising from multiple sources by a one-time operation comprises invoking a page fault handler to determine an address translation.

公开(公告)号：US20180089099A1

公开(公告)日：2018-03-29

申请号：US15280965

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Ashok RAJ ,  Sivakumar RADHAKRISHNAN ,  Dan J. WILLIAMS ,  Vishal VERMA ,  Narayan RANGANATHAN ,  Chet R. DOUGLAS

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/65

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

公开(公告)号：US20170286210A1

公开(公告)日：2017-10-05

申请号：US15087797

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Theodros YIGZAW ,  Ashok RAJ ,  Robert SWANSON ,  Mohan J. KUMAR

IPC: G06F11/07 ,  G06F12/08

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1064 ,  G06F12/0804 ,  G06F12/0811 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7201

Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

公开(公告)号：US20220350639A1

公开(公告)日：2022-11-03

申请号：US17651906

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Ashok RAJ ,  Rajesh SANKARAN

IPC: G06F9/48 ,  G06F9/30 ,  G06F13/28

Abstract: A processing device is provided. The processing device comprises an interface configured to receive information about an operation state of a surrogate processor. Further, the processing device comprises a processing circuitry configured to control the interface and to decide whether an interrupt addressed to the processing circuitry is processed by the processing circuitry or redirected to the surrogate processing circuitry based on an operation state of the processing circuitry and the surrogate processing circuitry.

公开(公告)号：US20210004334A1

公开(公告)日：2021-01-07

申请号：US16772765

申请日：2018-03-28

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Xiao ZHENG ,  Ashok RAJ ,  Sanjay KUMAR ,  Rajesh SANKARAN

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

公开(公告)号：US20190297015A1

公开(公告)日：2019-09-26

申请号：US16435328

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L12/747 ,  G06F13/28 ,  H04L12/773 ,  G06F12/1081 ,  H04L12/861

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20210112003A1

公开(公告)日：2021-04-15

申请号：US17129756

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L12/747 ,  G06F13/28 ,  H04L12/861 ,  G06F12/1081 ,  H04L12/773

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20220197805A1

公开(公告)日：2022-06-23

申请号：US17479954

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Anjali Singhai JAIN ,  Patrick MALONEY ,  Yadong LI ,  Chih-Jen CHANG ,  Kun TIAN ,  Yan ZHAO ,  Rajesh M. SANKARAN ,  Ashok RAJ

IPC: G06F12/0831 ,  G06F12/1009 ,  G06F9/455

Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: in connection with a request from a device to copy data to a destination memory address: based on a page fault, copy the data to a backup page and after determination of a virtual-to-physical address translation, copy the data from the backup page to a destination page identified by the physical address. In some examples, the copy the data to a backup page is based on a page fault and an indication that a target buffer for the data is at or above a threshold level of fullness. In some examples, copying the data to a backup page includes: receive the physical address of the backup page from the device and copy data from the device to the backup page based on identification of the backup page.

公开(公告)号：US20190205058A1

公开(公告)日：2019-07-04

申请号：US16326116

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Yao JIN ,  Ashok RAJ ,  Anthony E.G. LUCK

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0631 ,  G06F3/067 ,  G06F11/00 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0862 ,  G06F13/1668 ,  G06F13/4027

Abstract: A computing system includes a plurality of nodes including a first node, the first node including at least one core, a memory controller, a node-track register (MSR), and a monitoring counter array including a plurality of counters. The memory controller is to access a plurality of bits of the node-track MSR to determine a subset of nodes to be tracked, wherein the subset of nodes includes the first node and a second node. The memory controller is further to allocate a first counter of the plurality of counters to track memory requests sent to a local system memory by the first node; and allocate a second counter of the plurality of counters to track a memory response associated with a memory request sent by the first node to the second node.