公开(公告)号：US20240160585A1

公开(公告)日：2024-05-16

申请号：US18419159

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F12/14 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/00

Abstract: A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

公开(公告)号：US20170004098A1

公开(公告)日：2017-01-05

申请号：US15039468

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Abstract translation: 共享存储器控制器用于通过数据链路从多个独立节点服务加载和存储从数据链路接收的操作，以提供对共享存储器资源的访问。 要允许多个独立节点中的每一个访问共享存储器资源的相应部分。 在数据链路上发送互连协议数据和存储器访问协议数据，可以定义和识别互连协议数据和存储器访问协议数据之间的转换。

公开(公告)号：US20220012189A1

公开(公告)日：2022-01-13

申请号：US17485360

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US20170046208A1

公开(公告)日：2017-02-16

申请号：US15178159

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F9/52 ,  G06F12/1081 ,  G06F9/46 ,  G06F13/40 ,  G06F13/16 ,  G11C14/00

CPC classification number: G06F9/52 ,  G06F3/0619 ,  G06F3/0661 ,  G06F3/0688 ,  G06F9/467 ,  G06F11/2017 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/32 ,  G06F13/4022 ,  G06F2212/1056 ,  G11C14/009

Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.

Abstract translation: 这里描述了一种用于提供数据一致性的装置。 该装置包括全局持久存储器。 使用包含输入/输出（I / O）语义和内存语义的协议来访问全局永久存储器。 该装置还包括反射存储区域。 反射的存储器区域是全局持久存储器的一部分，并且多个节点的每个节点将反射的存储器区域映射到不可高速缓存的空间中。 此外，该装置包括信号量存储器。 信号量存储器为强制数据一致性提供硬件辅助。

公开(公告)号：US09372752B2

公开(公告)日：2016-06-21

申请号：US14142726

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/08 ,  G06F15/16

CPC classification number: G06F11/2094 ,  G06F11/108 ,  G06F11/1088 ,  G06F11/2043 ,  G06F11/2087 ,  G06F11/2092 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/0833 ,  G06F12/0837 ,  G06F15/16 ,  G06F2201/805 ,  G06F2201/82

Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.

Abstract translation: 本文描述了跨多个集群的相干共享存储器的装置。 该装置包括织物存储器控制器和一个或多个节点。 织物存储器控制器管理对每个节点的共享存储器区域的访问，使得即使响应于节点的故障，每个共享存储器区域也可以使用加载存储器语义来访问。 该设备还包括全局存储器，其中每个共享存储器区域被结构存储器控制器映射到全局存储器。

公开(公告)号：US11086520B2

公开(公告)日：2021-08-10

申请号：US16510106

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Mark A. Schmisseur ,  Mohan J. Kumar ,  Balint Fleischer ,  Debendra Das Sharma ,  Raj K. Ramanujan

IPC: G06F3/06 ,  H04L29/08 ,  H04L12/24

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

公开(公告)号：US09823849B2

公开(公告)日：2017-11-21

申请号：US14752812

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Mark A. Schmisseur ,  Mohan J. Kumar ,  Balint Fleischer ,  Debendra Das Sharma ,  Raj K. Ramanujan

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0685

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

公开(公告)号：US20170052860A1

公开(公告)日：2017-02-23

申请号：US15176185

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/108 ,  G06F11/1088 ,  G06F11/2043 ,  G06F11/2087 ,  G06F11/2092 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/0833 ,  G06F12/0837 ,  G06F15/16 ,  G06F2201/805 ,  G06F2201/82

Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.

Abstract translation: 本文描述了跨多个集群的相干共享存储器的装置。 该装置包括织物存储器控制器和一个或多个节点。 织物存储器控制器管理对每个节点的共享存储器区域的访问，使得即使响应于节点的故障，每个共享存储器区域也可以使用加载存储器语义来访问。 该设备还包括全局存储器，其中每个共享存储器区域被结构存储器控制器映射到全局存储器。

公开(公告)号：US10296399B2

公开(公告)日：2019-05-21

申请号：US15178159

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F11/00 ,  G06F9/52 ,  G06F3/06 ,  G06F11/20 ,  G06F13/32 ,  G06F12/0815 ,  G06F9/46 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/40 ,  G11C14/00 ,  G06F12/0817

Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.

公开(公告)号：US10229024B2

公开(公告)日：2019-03-12

申请号：US15176185

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G06F12/08 ,  G06F15/16 ,  G06F12/0837 ,  G06F12/0831

Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.