公开(公告)号：US20200220024A1

公开(公告)日：2020-07-09

申请号：US16640469

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Cory E. Weber ,  Sean T. Ma ,  Tahir Ghani ,  Shriram Shivaraman ,  Gilbert Dewey

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/51 ,  H01L29/792 ,  H01L27/108

Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.

公开(公告)号：US11515420B2

公开(公告)日：2022-11-29

申请号：US16643927

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Dax M. Crum ,  Cory E. Weber ,  Rishabh Mehandru ,  Harold Kennel ,  Benjamin Chu-Kung

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/417 ,  H01L29/08 ,  H01L29/165 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L29/267

Abstract: An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.

公开(公告)号：US10910405B2

公开(公告)日：2021-02-02

申请号：US16785986

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Patrick Morrow ,  Stephen M. Cea ,  Rishabh Mehandru ,  Cory E. Weber

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/84 ,  H01L21/306

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US10411090B2

公开(公告)日：2019-09-10

申请号：US15745417

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Rishabh Mehandru ,  Stephen M. Cea

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66

Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.

公开(公告)号：US10304946B2

公开(公告)日：2019-05-28

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Ranjith Kumar ,  Cory E. Weber ,  Seiyon Kim ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L27/11

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US09231076B2

公开(公告)日：2016-01-05

申请号：US14582391

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Mark Y. Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

公开(公告)号：US11990476B2

公开(公告)日：2024-05-21

申请号：US17842450

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Harold W. Kennel ,  Willy Rachmady ,  Gilbert Dewey

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02609

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：US20240008255A1

公开(公告)日：2024-01-04

申请号：US18325492

申请日：2023-05-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy ,  Cory E. Weber ,  Rishabh Mehandru ,  Wilfred Gomes ,  Pushkar Sharad Ranade

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/05 ,  H10B12/482

Abstract: Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

公开(公告)号：US11264453B2

公开(公告)日：2022-03-01

申请号：US16412305

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Aaron D. Lilak ,  Szuya S. Liao ,  Aaron A. Budrevich

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/775

Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.

公开(公告)号：US11222947B2

公开(公告)日：2022-01-11

申请号：US15757251

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Aaron D. Lilak ,  Szuya S. Liao ,  Aaron A. Budrevich

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/775

Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.