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    NON-VOLATILE MEMORY STRUCTURES AND DEVICES
    1.
    发明申请
    NON-VOLATILE MEMORY STRUCTURES AND DEVICES 审中-公开

    公开(公告)号：US20190044063A1

    公开(公告)日：2019-02-07

    申请号：US15942281

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Lorenzo Fratin ,  Russell L. Meyer ,  Fabio Pellizzer

    IPC: H01L45/00

    Abstract: A memory cell can include a chalcogenide material having a narrowed end. A conductive material can be positioned at the narrowed end of the chalcogenide material. A dielectric barrier layer can be disposed between the conductive material and the narrowed end of the chalcogenide material. A dielectric spacer material can be positioned along a narrowed segment of the chalcogenide material.

    Memory device with double protective liner
    4.
    发明授权
    Memory device with double protective liner 有权

    公开(公告)号：US11647638B2

    公开(公告)日：2023-05-09

    申请号：US16295687

    申请日：2019-03-07

    Applicant: INTEL CORPORATION

    Inventor： Anna Maria Conti ,  Fabio Pellizzer ,  Agostino Pirovano ,  Kolya Yastrebenetsky

    IPC: H01L23/528 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

    Abstract: A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.

    Memory device with increased electrode resistance to reduce transient selection current
    5.
    发明授权
    Memory device with increased electrode resistance to reduce transient selection current 有权

    公开(公告)号：US11264567B2

    公开(公告)日：2022-03-01

    申请号：US16688309

    申请日：2019-11-19

    Applicant: INTEL CORPORATION

    Inventor： Srivatsan Venkatesan ,  Davide Mantegazza ,  John Gorman ,  Iniyan Soundappa Elango ,  Davide Fugazza ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

    Multi-deck memory device with inverted deck
    6.
    发明授权
    Multi-deck memory device with inverted deck 有权

    公开(公告)号：US10163982B2

    公开(公告)日：2018-12-25

    申请号：US15474154

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Fabio Pellizzer ,  Agostino Pirovano ,  DerChang Kau

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  G11C13/00

    Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.

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