公开(公告)号：US20250105053A1

公开(公告)日：2025-03-27

申请号：US18473711

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Han Wui Then ,  Feras Eid ,  James E. Jaussi ,  Ganesh Balamurugan ,  Thomas L. Sounart ,  Johanna Swan ,  Henning Braunisch ,  Tushar Kanti Talukdar ,  Shawna M. Liff

IPC: H01L21/762 ,  G02B6/30 ,  G02B6/43 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or electronic integrated circuits. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US12205902B2

公开(公告)日：2025-01-21

申请号：US17388964

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H05K1/18

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US12126067B2

公开(公告)日：2024-10-22

申请号：US16911559

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Diego Correas-Serrano ,  Georgios Dogiamis ,  Henning Braunisch ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing

IPC: H01P3/16 ,  H01P1/20 ,  H01P1/208 ,  H01P5/08

CPC classification number: H01P3/16 ,  H01P1/2002 ,  H01P1/2088 ,  H01P5/087

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US12088360B2

公开(公告)日：2024-09-10

申请号：US16897135

申请日：2020-06-09

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Diego Correas-Serrano ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing ,  Cooper S. Levy ,  Chintan S. Thakkar ,  Stefano Pellerano

IPC: H04B3/32 ,  H04L25/03

CPC classification number: H04B3/32 ,  H04L25/03885

Abstract: Embodiments may relate to a baseband module with communication pathways for a first data signal and a second data signal. The baseband module may also include a finite impulse response (FIR) filter in a communication path between the first signal input and the second signal output. Other embodiments may be described or claimed.

公开(公告)号：US20240063120A1

公开(公告)日：2024-02-22

申请号：US17820961

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Debendra Mallik ,  Christopher M. Pelto ,  Kimin Jun ,  Johanna M. Swan ,  Lei Jiang ,  Feras Eid ,  Krishna Vasanth Valavala ,  Henning Braunisch ,  Patrick Morrow ,  William J. Lambert

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC classification number: H01L23/5286 ,  H01L24/08 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0652 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5226 ,  H01L24/80 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16225

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.

公开(公告)号：US20240061194A1

公开(公告)日：2024-02-22

申请号：US17821019

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  David Hui ,  Haris Khan Niazi ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Henning Braunisch ,  Shawna M. Liff ,  Jiraporn Seangatith ,  Johanna M. Swan ,  Krishna Vasanth Valavala ,  Xavier Francois Brun ,  Feras Eid

IPC: G02B6/42

CPC classification number: G02B6/4274 ,  G02B6/4204

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.

公开(公告)号：US20210408653A1

公开(公告)日：2021-12-30

申请号：US16911568

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Diego Correas-Serrano ,  Georgios Dogiamis ,  Henning Braunisch ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing

IPC: H01P3/16 ,  H01P1/20 ,  H01P5/08 ,  H01P1/208

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US20210398895A1

公开(公告)日：2021-12-23

申请号：US16907797

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Beomseok Choi ,  Henning Braunisch ,  William Lambert ,  Krishna Bharath ,  Johanna Swan

IPC: H01L23/50 ,  H05K1/18 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

公开(公告)号：US20200303327A1

公开(公告)日：2020-09-24

申请号：US16394514

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Henning Braunisch

IPC: H01L23/66 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L25/00

Abstract: Embodiments may relate to a microelectronic package that includes a substrate signal path and a waveguide. The package may further include dies that are communicatively coupled with one another by the substrate signal path and the waveguide. The substrate signal path may carry a signal with a frequency that is different than the frequency of a signal that is to be carried by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US20200296823A1

公开(公告)日：2020-09-17

申请号：US16399024

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Johanna M. Swan ,  Georgios Dogiamis ,  Henning Braunisch ,  Adel A. Elsherbini ,  Aleksandar Aleksov

IPC: H05K1/02 ,  H01L23/66 ,  H01P5/08

Abstract: Embodiments may relate to an electronic module for use in an electronic device. The electronic module may include a printed circuit board (PCB) with a first die and a second die. A waveguide channel may be communicatively coupled with the first die and the second die and configured to convey an electromagnetic signal from the first die to the second die. In embodiments, the electromagnetic signal may have a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.