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公开(公告)号：US10649832B2
公开(公告)日：2020-05-12
申请号：US15677325
申请日：2017-08-15
Applicant: Intel Corporation
Inventor： Kasper Wszolek , Janusz P. Jurski , Piotr Kwidzinski , Robert C. Swanson , Madhusudhan Rangarajan
Abstract: Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.
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公开(公告)号：US09880859B2
公开(公告)日：2018-01-30
申请号：US14226223
申请日：2014-03-26
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Mallik Bulusu , Vincent J. Zimmer , Robert W. Cone , Robert B. Bahnsen
CPC classification number: G06F9/4416
Abstract: Technologies for managing image discovery includes a server controller to cause a server to enter a pre-boot state. The server controller communicates with the server while the server maintains the pre-boot state to determine identification data of the server in response to a transitioning the server to the pre-boot state. The server controller identifies a boot image of the server based on the identification data of the server and associates the server with the identified boot image.
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公开(公告)号：US20170010991A1
公开(公告)日：2017-01-12
申请号：US15270151
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC: G06F13/24 , G11C7/10 , G11C11/406
CPC classification number: G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的体系结构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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4.发明授权公开(公告)号：US09477564B2
公开(公告)日：2016-10-25
申请号：US14310835
申请日：2014-06-20
Applicant: INTEL CORPORATION
Inventor： Robert C. Swanson , Robert W. Cone , Malay Trivedi
CPC classification number: G06F11/2033 , G06F11/1428 , G06F11/2002 , G06F13/4027 , G06F13/4221 , G06F2201/845 , G06F2201/85
Abstract: Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.
Abstract translation: 多节点环境中动态节点愈合的方法和装置。 多节点平台控制器集线器（MN-PCH）被配置为通过使用专用接口和组件以及共享功能来支持多个节点。 接口和组件可以被配置为由相应节点使用，或者可以被配置为支持作为冗余主要和备用接口和组件的增强的弹性。 为了响应检测到故障或故障的主接口或组件，MN-PCH自动执行故障切换操作，以将备用主机替换为备用。 此外，故障切换操作对于在平台节点上运行的操作系统是透明的。
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5.发明授权Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM 有权在处理器中提供状态存储器，用于通过寄存器位而不是外部SMRAM选择性地启用系统管理模式公开(公告)号：US09465647B2
公开(公告)日：2016-10-11
申请号：US14048451
申请日：2013-10-08
Applicant: INTEL CORPORATION
Inventor： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
CPC classification number: G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US10324852B2
公开(公告)日：2019-06-18
申请号：US15374796
申请日：2016-12-09
Applicant: INTEL CORPORATION
Inventor： Theodros Yigzaw , Ashok Raj , Robert C. Swanson , Mohan J. Kumar
IPC: G06F11/00 , G06F12/0868 , G06F11/20 , G06F12/109
Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.
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公开(公告)号：US20180165207A1
公开(公告)日：2018-06-14
申请号：US15374796
申请日：2016-12-09
Applicant: INTEL CORPORATION
Inventor： Theodros Yigzaw , Ashok Raj , Robert C. Swanson , Mohan J. Kumar
IPC: G06F12/0868 , G06F11/20 , G06F12/109
CPC classification number: G06F12/0868 , G06F11/2094 , G06F12/0804 , G06F12/0866 , G06F12/109 , G06F2201/805 , G06F2201/82 , G06F2212/1032 , G06F2212/202 , G06F2212/2022 , G06F2212/222
Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.
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公开(公告)号：US09798641B2
公开(公告)日：2017-10-24
申请号：US14978597
申请日：2015-12-22
Applicant: Intel Corporation
Inventor： Robert C. Swanson , Theodros Yigzaw , Eswaramoorthi Nallusamy , Raghunandan Makaram , Vincent J. Zimmer
CPC classification number: G06F11/263 , G06F1/24 , G06F11/073 , G06F11/0793 , G06F11/1016 , G06F21/53 , G06F2221/034
Abstract: Methods and apparatus to increase cloud availability and silicon isolation using secure enclaves. A compute platform is configured to host a compute domain in which a plurality of secure enclaves are implemented. In conjunction with creating and deploying secure enclaves, mapping information is generated that maps the secure enclaves to platform/CPU resources, such as Intellectual Property blocks (IP) belong to the secure enclaves. In response to platform error events caused by errant platform/CPU resources, the secure enclave(s) belonging to the errant platform/CPU are identified via the mapping information, and an interrupt is directed to that/those secure enclave(s). In response to the interrupt, a secure enclave may be configured to one or more of handle the error, pass information to another secure enclave, and teardown the enclave. The secure enclave may execute an interrupt service routine that causes the errant platform/CPU resource to reset without resetting the entire platform or CPU, as applicable.
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公开(公告)号：US20160065573A1
公开(公告)日：2016-03-03
申请号：US14938223
申请日：2015-11-11
Applicant: Intel Corporation
Inventor： Mallik Bulusu , Robert Bruce Bahnsen , Vincent J. Zimmer , Robert S. Gittins , Robert C. Swanson
CPC classification number: H04L63/0876 , G06F21/00 , H04L63/08 , H04W12/06 , H04W12/08
Abstract: An embodiment includes a secure and stable method for sending information across a compute continuum. For example, the method may include executing an application (e.g., video player) on a first node (e.g., tablet) with a desire to perform “context migration” to a second node (e.g., desktop). This may allow a user to watch a movie on the tablet, stop watching the movie, and then resume watching the movie from the desktop. To do so in a secure and stable manner, the first node may request security and performance credentials from the second node. If both credential sets satisfy thresholds, the first node may transfer content (e.g., encrypted copy of a movie) and state information (e.g., placeholder indicating where the movie was when context transfer began). The second node may then allow the user to resume his or her movie watching from the desktop. Other embodiments are described herein.
Abstract translation: 一个实施例包括用于在计算连续体上发送信息的安全且稳定的方法。 例如，该方法可以包括在第一节点（例如，平板电脑）上执行应用（例如，视频播放器），期望执行到第二节点（例如桌面）的“上下文迁移”。 这可能允许用户在平板电脑上观看电影，停止观看电影，然后从桌面恢复观看电影。 为了以安全和稳定的方式这样做，第一节点可以从第二节点请求安全性和性能凭证。 如果两个凭证组都满足阈值，则第一节点可以传送内容（例如，电影的加密副本）和状态信息（例如，当上下文传送开始时，指示电影在哪里的占位符）。 然后，第二节点可以允许用户从桌面恢复他或她的电影观看。 本文描述了其它实施例。
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10.发明申请公开(公告)号：US20150370661A1
公开(公告)日：2015-12-24
申请号：US14310835
申请日：2014-06-20
Applicant: INTEL CORPORATION
Inventor： Robert C. Swanson , Robert W. Cone , Malay Trivedi
CPC classification number: G06F11/2033 , G06F11/1428 , G06F11/2002 , G06F13/4027 , G06F13/4221 , G06F2201/845 , G06F2201/85
Abstract: Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.
Abstract translation: 多节点环境中动态节点愈合的方法和装置。 多节点平台控制器集线器（MN-PCH）被配置为通过使用专用接口和组件以及共享功能来支持多个节点。 接口和组件可以被配置为由相应节点使用，或者可以被配置为支持作为冗余主要和备用接口和组件的增强的弹性。 为了响应检测到故障或故障的主接口或组件，MN-PCH自动执行故障切换操作，以将备用主机替换为备用。 此外，故障切换操作对于在平台节点上运行的操作系统是透明的。
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